@@ -2067,7 +2067,7 @@ void cdabs(ref CGstate cg, ref CodeBuilder cdb,elem* e, ref regm_t pretregs)
20672067 {
20682068 /* Generate:
20692069 FMOV Xn,Vn.d[1] // upper 64 bits
2070- EOR Xn,Xn,#0x8000_0000_0000_0000 // toggle sign bit
2070+ AND Xn,Xn,#0x7FFF_FFFF_FFFF_FFFF // clear sign bit
20712071 FMOV Vn.d[1],Xn // store upper 64 bits
20722072 */
20732073 // Alloc Xn
@@ -2076,8 +2076,8 @@ void cdabs(ref CGstate cg, ref CodeBuilder cdb,elem* e, ref regm_t pretregs)
20762076 // https://www.scs.stanford.edu/~zyedidia/arm64/fmov_float_gen.html
20772077 cdb.gen1(INSTR .fmov_float_gen(1 ,2 ,1 ,6 ,Vn,Xn)); // Top half of 128-bit to 64-bit
20782078 uint N, immr, imms;
2079- assert (encodeNImmrImms(0x8000_0000_0000_0000 ,N,immr,imms));
2080- uint sf = 1 , opc = 2 ;
2079+ assert (encodeNImmrImms(0x7FFF_FFFF_FFFF_FFFF ,N,immr,imms));
2080+ uint sf = 1 , opc = 0 ;
20812081 cdb.gen1(INSTR .log_imm(sf,opc,N,immr,imms,Xn,Xn)); // https://www.scs.stanford.edu/~zyedidia/arm64/eor_log_imm.html
20822082 cdb.gen1(INSTR .fmov_float_gen(1 ,2 ,1 ,7 ,Xn,Vn)); // 64-bit to top half of 128-bit
20832083 }
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