One import statement per module (#144)

Author: Paebbels

pyEDAA/ProjectModel/Xilinx/Vivado.py

@@ -29,19 +29,17 @@
 # ==================================================================================================================== #
 #
 """Specific file types and attributes for Xilinx Vivado."""
-from pathlib import Path
-from typing  import Iterable, Optional as Nullable
-from xml.dom import minidom, Node
+from pathlib               import Path
+from typing                import Iterable, Optional as Nullable
+from xml.dom               import minidom, Node
 
 from pyTooling.Decorators  import export
 from pyTooling.MetaClasses import ExtendedType
 from pyVHDLModel           import VHDLVersion
 
-from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design
-from pyEDAA.ProjectModel import File as Model_File
-from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile
-from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile
-from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile
+from pyEDAA.ProjectModel   import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design, \
+                                  File as Model_File, ConstraintFile as Model_ConstraintFile, \
+                                  VerilogSourceFile as Model_VerilogSourceFile, VHDLSourceFile as Model_VHDLSourceFile
 
 
 @export

pyEDAA/ProjectModel/__init__.py

@@ -40,9 +40,10 @@
 __documentation_url__ = "https://edaa-org.github.io/pyEDAA.ProjectModel"
 __issue_tracker_url__ = "https://GitHub.com/edaa-org/pyEDAA.ProjectModel/issues"
 
-from os.path import relpath as path_relpath
-from pathlib import Path as pathlib_Path
-from typing  import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Self
+from os.path               import relpath as path_relpath
+from pathlib               import Path as pathlib_Path
+from typing                import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, \
+                                  Any as typing_Any, Type, Set, Self
 
 from pyTooling.Common      import getFullyQualifiedName
 from pyTooling.Decorators  import export

tests/unit/Files.py

@@ -36,7 +36,8 @@
 from pySVModel           import SystemVerilogVersion
 from pyVHDLModel         import VHDLVersion
 
-from pyEDAA.ProjectModel import FileSet, VHDLSourceFile, VHDLLibrary, VerilogSourceFile, SystemVerilogSourceFile, FileTypes, Project, Design
+from pyEDAA.ProjectModel import FileSet, VHDLSourceFile, VHDLLibrary, VerilogSourceFile, SystemVerilogSourceFile, \
+                                FileTypes, Project, Design
 
 
 if __name__ == "__main__": # pragma: no cover