f-strings without placeholder are plain strings.

9 f-strings had no placeholder, so their 'f' prefix did nothing; 'f"…"' becomes '"…"', escaped braces '{{'/'}}'
become '{'/'}'. Every string keeps its value. Fixed with CheckNeedlessFStrings (pyflakes F541).

Co-Authored-By: Patrick Lehmann <Paebbels@gmail.com>

Author: claude-code

doc/conf.py

@@ -209,12 +209,12 @@
 # Sphinx.Ext.ExtLinks
 # ==============================================================================
 extlinks = {
-	"gh":          (f"https://GitHub.com/%s", "%s"),
+	"gh":          ("https://GitHub.com/%s", "%s"),
 	"ghissue":     (f"https://GitHub.com/{githubNamespace}/{project}/issues/%s", "issue #%s"),
 	"ghpull":      (f"https://GitHub.com/{githubNamespace}/{project}/pull/%s", "pull request #%s"),
 	"ghsrc":       (f"https://GitHub.com/{githubNamespace}/{project}/blob/main/%s", None),
 	"pypi":        ("https://PyPI.org/project/%s", "%s"),
-	"wiki":        (f"https://en.wikipedia.org/wiki/%s", None),
+	"wiki":        ("https://en.wikipedia.org/wiki/%s", None),
 }
 
 

pyEDAA/ProjectModel/__init__.py

@@ -433,14 +433,14 @@ def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] =
 				except KeyError as ex:
 					raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex
 			else:
-				raise Exception(f"Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.")
+				raise Exception("Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.")
 		elif isinstance(vhdlLibrary, VHDLLibrary):
 			self._vhdlLibrary = vhdlLibrary
 			vhdlLibrary.AddFile(self)
 		elif vhdlLibrary is None:
 			self._vhdlLibrary = None
 		else:
-			ex = TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
+			ex = TypeError("Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
 			ex.add_note(f"Got type '{getFullyQualifiedName(vhdlLibrary)}'.")
 			raise ex
 
@@ -917,11 +917,11 @@ def AddFile(self, file: File) -> None:
 			raise TypeError("Parameter 'file' is not of type ProjectModel.File.")
 		elif file._fileSet is not None:
 			ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.")
-			ex.add_note(f"A file can't be assigned to another fileset.")
+			ex.add_note("A file can't be assigned to another fileset.")
 			raise ex
 		elif file in self._set:
 			ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.")
-			ex.add_note(f"A file can't be added twice to a fileset.")
+			ex.add_note("A file can't be added twice to a fileset.")
 			raise ex
 
 		self._files.append(file)
@@ -1254,7 +1254,7 @@ def AddDependency(self, library: 'VHDLLibrary') -> None:
 
 	def AddFile(self, vhdlFile: VHDLSourceFile) -> None:
 		if not isinstance(vhdlFile, VHDLSourceFile):
-			ex = TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
+			ex = TypeError("Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
 			ex.add_note(f"Got type '{getFullyQualifiedName(vhdlFile)}'.")
 			raise ex
 

tests/unit/DependencyScan.py

@@ -76,7 +76,7 @@ def test_VHDLLibrary(self) -> None:
 		print(f"Loading design '{designA.Name}':")
 		design = DOMDesign(name=designA.Name)
 
-		print(f"  Loading default libraries (Std, Ieee, ...)")
+		print("  Loading default libraries (Std, Ieee, ...)")
 		design.LoadDefaultLibraries()
 
 		for libraryName, vhdlLibrary in designA.VHDLLibraries.items():
@@ -97,7 +97,7 @@ def test_VHDLLibrary(self) -> None:
 
 				design.AddDocument(vhdlDocument, lib)
 
-		print(f"  Analyzing design ...")
+		print("  Analyzing design ...")
 		design.Analyze()
 
 		print()