loader.c

#define DEBUG_BUILD 0

#if(DEBUG_BUILD)
#define DEBUG_MARKER(X) \
    __asm__ volatile ( \
        "marker_" #X "_start:\n\t" \
        "    j marker_" #X "_end\n\t" \
        "    nop\n\t" \
        "    nop\n\t" \
        "    .word " #X "\n\t" \
        "    nop\n\t" \
        "marker_" #X "_end:\n\t" \
        "    nop\n\t" \
    )
#else
#define DEBUG_MARKER(X)
#endif

#include "loader.h"
#include "mcu.h"
#include "spi_flash.h"

//========== Primary loader functions ==========
static void loader_init_mcu_clock_config(void);
static void loader_init_qspi_configure_spi_cmd(CTRL *LDR);
static void loader_init_qspi_test(CTRL *LDR);
static void loader_execute_request(CTRL *LDR);
static void loader_flash_read(CTRL *LDR);
static void loader_flash_write(CTRL *LDR);
static void loader_flash_erase(CTRL *LDR);

//========== Helper functions ==========
static void mcu_wait_int_decrement(unsigned long wait_len);
static void qspi_rx_clear(void);
static void qspi_write_read(unsigned long write_len, unsigned char *write_data,
		unsigned long read_len, unsigned char *read_data_out);
static void qspi_write_write(unsigned long write_len, unsigned char *write_data,
		unsigned long write_2_len, unsigned char *write_2_data);
static void qspi_cmd_write(unsigned char cmd);
static void qspi_register_read(unsigned char cmd, unsigned char *reg_val_out);
static void qspi_register_write(unsigned char cmd, unsigned char new_reg_val);

//========== ENTRY POINT ==========

__attribute__((used))
__attribute__((naked))
__attribute__((noinline))
void loader() {
	asm volatile(
			"auipc a0, 0\n"
			"jal x0, loader_entry\n"

			".align 2\n"                // 4-byte alignment
			"loader_config_table:\n"
			".word %0\n"
			".word %3\n"
			".word 0x00000000\n"
			".word 0x00000000\n"
			".word %4\n"
			".word %5\n"
			".word %1\n"
			".word %2\n"
			".word %6\n"
			".word %7\n"
			".zero 32\n"

			"loader_entry:\n"
			"la t0, loader_config_table\n"

			"lw sp, 0(t0)\n"
			"add sp, sp, a0\n"
			:
			: "i"(STACK_OFFSET),
			"i"(FLASH_ADDR),
			"i"(FLASH_SIZE),
			"i"(RAM_OFFSET),
			"i"(RQX_INIT),
			"i"(ERR_INIT),
			"i"(LOADER_VERSION_MAJOR),
			"i"(LOADER_VERSION_MINOR)
	);

	__asm__ volatile("add a0, t0, x0");
	__asm__ volatile("addi sp, sp, -16");
	__asm__ volatile("sw a0, 0(sp)");

	__asm__ volatile("jal ra, loader_init_mcu_clock_config");
	DEBUG_MARKER(0x06);

	__asm__ volatile("lw a0, 0(sp)");
	__asm__ volatile("jal ra, loader_init_qspi_configure_spi_cmd");
	DEBUG_MARKER(0x07);

	__asm__ volatile("lw a0, 0(sp)");
	__asm__ volatile("jal ra, loader_init_qspi_test");
	DEBUG_MARKER(0x08);

	__asm__ volatile("request_loop:");
	__asm__ volatile("lw a0, 0(sp)");
	__asm__ volatile("jal ra, loader_execute_request");
	DEBUG_MARKER(0x09);
	__asm__ volatile("j request_loop");

}



//========== Loader functions ==========


__attribute__((used))
__attribute__((noinline))
static void loader_init_mcu_clock_config(void) {
	FE310_PRCI *PRCI = (FE310_PRCI*) FE310_PRCI_BASE;

	PRCI->hfxosccfg = 1 << 30;  //Activate XTAL (16MHz)
	while (!(PRCI->hfxosccfg & (1 << 31))); //Wait until XTAL is ready

	PRCI->pllcfg |= 1UL << 18; //PLL off
	PRCI->pllcfg |= 1UL << 17; //PLLREFSEL from XTAL

	//Set PLLR (divides XTAL Freq, output 8MHz, must be 6-12)
	PRCI->pllcfg = (PRCI->pllcfg & ~0x07) | (1);
	//Set PLLF (multiplies PLLR, output 480MHz, must be 384-768)
	PRCI->pllcfg = (PRCI->pllcfg & ~0x03F0) | (29 << 4); //For 320: 39, for 288MHz: 35, for 240MHz: 29
	//Set PLLQ (divides PLLF, output 240MHz, must be 48-384)
	PRCI->pllcfg = (PRCI->pllcfg & ~(0x03 << 10)) | (1 << 10);
	//Set PLLOUTDIV to 1
	PRCI->plloutdiv = 1UL << 8;
	__asm__ volatile ("" ::: "memory");

	PRCI->pllcfg &= ~(1UL << 18);  //PLLBYPASS use PLL

	mcu_wait_int_decrement(20000);  //Wait until PLL is stable and ready for use
	while (!(PRCI->pllcfg & (1UL << 31)));

	//PLLSEL PLL output from PLL and not from interal OSC
	PRCI->pllcfg |= 1UL << 16;
	DEBUG_MARKER(0x19);

}


__attribute__((used))
__attribute__((noinline))
static void loader_init_qspi_configure_spi_cmd(CTRL *LDR) {
	FE310_SPI *QSPI = (FE310_SPI*) FE310_QSPI_BASE;

	QSPI->fctrl = 0;  // Disable memory-mapped mode
	QSPI->csid = 0;  // Select CS0, auto mode
	QSPI->sckdiv = 2;  // clkout = clkin/(2*(div+1))
	QSPI->sckmode = 0; //pol = 0, pha = 0
	QSPI->csid = 0;  //cs pin 0
	QSPI->csdef = ~(0UL);  //cs inactive state
	QSPI->csmode = QSPI_CSMODE_OFF;//0 = auto, 2 = hold, 3 = off
	QSPI->delay0 = 1UL | (1UL << 16);  //delay between cs and sck
	QSPI->delay1 = 1UL | (1UL << 16);  //delay between cs activations, how long cs is asserted
	//frame format:	SPI (1 line), MSB first, dir = 0, len = 8
	QSPI->fmt = QSPI_FMT_BUS_WIDTH_1 | (0UL << 2) | (0UL << 3) | (8UL << 16);
	DEBUG_MARKER(0x27);

	// ========== CONFIGURE FLASH ==========
	LDR->ERR = ERRCODE_FAILED_TO_INIT_FLASH_SPI_MODE;
	unsigned char flash_status_reg = 0xFF;

	QSPI->fmt &= ~QSPI_FMT_BUS_WIDTH_MSK;
	QSPI->fmt |= QSPI_FMT_BUS_WIDTH_4;
	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_RESET_ENABLE);
	mcu_wait_int_decrement(5000);
	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_RESET_MEMORY);
	mcu_wait_int_decrement(5000);
	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_QPID);
	mcu_wait_int_decrement(5000);
	QSPI->fmt &= ~QSPI_FMT_BUS_WIDTH_MSK;
	QSPI->fmt |= QSPI_FMT_BUS_WIDTH_1;
	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_RESET_ENABLE);
	mcu_wait_int_decrement(5000);
	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_RESET_MEMORY);
	mcu_wait_int_decrement(5000);
	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_WRITE_ENABLE);
	mcu_wait_int_decrement(5000);
	qspi_register_write(JEDEC_SPI_FLASH_CMD_WRITE_STATUS_REG, 0);
	mcu_wait_int_decrement(5000);
	while (flash_status_reg) {
		qspi_register_read(JEDEC_SPI_FLASH_CMD_READ_STATUS_REG1,
				&flash_status_reg);
		LDR->FLASH_INIT_STATUS_REG = flash_status_reg;
		mcu_wait_int_decrement(10000);
		DEBUG_MARKER(0x28);
	}
	LDR->ERR = ERRCODE_OK;

	DEBUG_MARKER(0x29);
}


__attribute__((used))
__attribute__((noinline))
static void loader_init_qspi_test(CTRL *LDR) {
	LDR->ERR = ERRCODE_FLASH_TEST_FAILED;
	unsigned char cmd = JEDEC_SPI_FLASH_CMD_READ_JEDEC_ID;
	qspi_write_read(1, &cmd, 3, (unsigned char*)&LDR->FLASH_JEDEC_ID[0]);
	LDR->ERR = ERRCODE_OK;
	DEBUG_MARKER(0x39);
}


__attribute__((used))
__attribute__((noinline))
static void loader_execute_request(CTRL *LDR) {
	unsigned long request = LDR->RQX;
	DEBUG_MARKER(0x41);
	if (request == RQX_NONE) {
		__asm__ volatile("ebreak\n"
				"c.nop\n"
				"c.nop\n"
				"c.nop\n"	//regardless of ebreak width, pc+4 is safe and valid
				"c.nop");
	}
	request = LDR->RQX;
	LDR->STATUS |= CTRL_STATUS_BUSY;
	switch (request) {
	case (RQX_FLASH_CONFIG_SPI_CMD):
		loader_init_qspi_configure_spi_cmd(LDR);
		break;
	case (RQX_FLASH_ERASE_CHIP):
	case (RQX_FLASH_ERASE_BLOCK_64KIB):
	case (RQX_FLASH_ERASE_SECTOR_4KIB):
		loader_flash_erase(LDR);
		break;
	case (RQX_FLASH_READ):
		loader_flash_read(LDR);
		break;
	case (RQX_FLASH_WRITE_PAGE):
		loader_flash_write(LDR);
		break;
	default:
		break;
	}
	LDR->STATUS &= ~CTRL_STATUS_BUSY;
	LDR->CMDCTR++;
	//crude prevention of overflow (not likely irl)
	if (LDR->CMDCTR >= ((unsigned long) ~0 - 100))
		LDR->CMDCTR = 0x80000000;
	LDR->RQX = RQX_NONE;
	DEBUG_MARKER(0x49);
}


__attribute__((used))
__attribute__((noinline))
static void loader_flash_read(CTRL *LDR) {
	struct __attribute__((packed)) {
		unsigned char cmd;
		unsigned char addr[3];
	} read_cmd;
	unsigned char *ram_destination =
			(((unsigned char*) LDR - LOADER_CTRL_OFFSET) + LDR->RMEMOFF);
	read_cmd.cmd = JEDEC_SPI_FLASH_CMD_READ_DATA;
	read_cmd.addr[0] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 16));
	read_cmd.addr[1] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 8));
	read_cmd.addr[2] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 0));
	qspi_write_read(4, &read_cmd.cmd, LDR->FMEMSIZE, ram_destination);
	DEBUG_MARKER(0x59);
}


__attribute__((used))
__attribute__((noinline))
static void loader_flash_write(CTRL *LDR) {
	struct __attribute__((packed)) {
		unsigned char cmd;
		unsigned char addr[3];
	} write_cmd;
	unsigned char *ram_source = (((unsigned char*) LDR - LOADER_CTRL_OFFSET)
			+ LDR->RMEMOFF);
	write_cmd.cmd = JEDEC_SPI_FLASH_CMD_PAGE_PROGRAM;
	write_cmd.addr[0] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 16));
	write_cmd.addr[1] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 8));
	write_cmd.addr[2] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 0));
	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_WRITE_ENABLE);
	mcu_wait_int_decrement(5000);
	qspi_write_write(4, &write_cmd.cmd, LDR->FMEMSIZE, ram_source);
	mcu_wait_int_decrement(5000);

	unsigned char flash_status_reg = 0xFF;
	while (flash_status_reg & JEDEC_SPI_FLASH_SR1_WIP_MSK) {
		qspi_register_read(JEDEC_SPI_FLASH_CMD_READ_STATUS_REG1,
				&flash_status_reg);
		mcu_wait_int_decrement(5000);
	}

	DEBUG_MARKER(0x69);
}


__attribute__((used))
__attribute__((noinline))
static void loader_flash_erase(CTRL *LDR) {
	struct __attribute__((packed)) {
		unsigned char cmd;
		unsigned char addr[3];
	} erase_cmd;
	unsigned long cmd_len = 1;

	erase_cmd.cmd = JEDEC_SPI_FLASH_CMD_CHIP_ERASE_1;
	if (LDR->RQX == RQX_FLASH_ERASE_BLOCK_64KIB)
		erase_cmd.cmd = JEDEC_SPI_FLASH_CMD_BLOCK_ERASE_64K;
	if (LDR->RQX == RQX_FLASH_ERASE_SECTOR_4KIB)
		erase_cmd.cmd = JEDEC_SPI_FLASH_CMD_SECTOR_ERASE_4K;
	if (erase_cmd.cmd != JEDEC_SPI_FLASH_CMD_CHIP_ERASE_1) {
		erase_cmd.addr[0] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 16));
		erase_cmd.addr[1] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 8));
		erase_cmd.addr[2] = (unsigned char) (0xFF & (LDR->FMEMADDR >> 0));
		cmd_len = 4;
	}

	qspi_cmd_write(JEDEC_SPI_FLASH_CMD_WRITE_ENABLE);
	qspi_write_write(cmd_len, &erase_cmd.cmd, 0, &erase_cmd.cmd);

	//wait until Write In Progress bit is reset
	unsigned char flash_status_reg = 0xFF;
	while (flash_status_reg & JEDEC_SPI_FLASH_SR1_WIP_MSK) {
		qspi_register_read(JEDEC_SPI_FLASH_CMD_READ_STATUS_REG1,
				&flash_status_reg);
		mcu_wait_int_decrement(5000);
	}

	DEBUG_MARKER(0x79);
}


//========== Helper functions ==========

__attribute__((used))
__attribute__((noinline))
static void mcu_wait_int_decrement(unsigned long wait_len) {
	DEBUG_MARKER(0x101);
	volatile unsigned long countdown = wait_len;
	for (; countdown > 0; countdown--);
}


__attribute__((used))
__attribute__((noinline))
static void qspi_rx_clear(void) {
	FE310_SPI *QSPI = (FE310_SPI*) FE310_QSPI_BASE;
	while (!((QSPI->rxdata) & (1UL << 31)));
}


__attribute__((used))
__attribute__((noinline))
static void qspi_write_read(unsigned long write_len, unsigned char *write_data,
		unsigned long read_len, unsigned char *read_data_out) {
	qspi_rx_clear();
	FE310_SPI *QSPI = (FE310_SPI*) FE310_QSPI_BASE;
	QSPI->txmark = 1UL;
	QSPI->rxmark = 0UL;
	QSPI->fmt &= ~(1UL << 3);
	QSPI->csmode = QSPI_CSMODE_HOLD;
	DEBUG_MARKER(0x501);
	for (unsigned long write_byte_index = 0; write_byte_index < write_len;
			write_byte_index++) {
		QSPI->txdatab[0] = write_data[write_byte_index];
		while (!(QSPI->ip & QSPI_IP_RX_WATERMARK_MSK));
		(void) QSPI->rxdata;
	}
	for (unsigned long read_byte_index = 0; read_byte_index < read_len;
			read_byte_index++) {
		QSPI->txdatab[0] = 0x00;
		while (!(QSPI->ip & QSPI_IP_RX_WATERMARK_MSK));
		read_data_out[read_byte_index] = (unsigned char) (QSPI->rxdata & 0xFF);
	}
	QSPI->csmode = QSPI_CSMODE_AUTO;
}


__attribute__((used))
__attribute__((noinline))
static void qspi_write_write(unsigned long write_len, unsigned char *write_data,
		unsigned long write_2_len, unsigned char *write_2_data) {
	qspi_rx_clear();
	FE310_SPI *QSPI = (FE310_SPI*) FE310_QSPI_BASE;
	QSPI->txmark = 1UL;
	QSPI->rxmark = 0UL;
	QSPI->fmt |= (1UL << 3);
	QSPI->csmode = QSPI_CSMODE_HOLD;
	DEBUG_MARKER(0x601);
	const unsigned long total_write_len = write_len + write_2_len;
	for (unsigned long write_index = 0; write_index < total_write_len;
			write_index++) {
		while (QSPI->txdata & (1UL << 31));
		if (write_index < write_len) {
			QSPI->txdatab[0] = write_data[write_index];
		} else {
			QSPI->txdatab[0] = write_2_data[write_index - write_len];
		}
	} DEBUG_MARKER(0x603);
	while ((QSPI->ip & QSPI_IP_TX_WATERMARK_MSK) == 0);
	QSPI->csmode = QSPI_CSMODE_AUTO;
}


__attribute__((used))
__attribute__((noinline))
static void qspi_cmd_write(unsigned char cmd) {
	qspi_write_write(1, &cmd, 0, &cmd);
}


__attribute__((used))
__attribute__((noinline))
static void qspi_register_read(unsigned char cmd, unsigned char *reg_val_out) {
	qspi_write_read(1, &cmd, 1, reg_val_out);
}


__attribute__((used))
__attribute__((noinline))
static void qspi_register_write(unsigned char cmd, unsigned char new_reg_val) {
	qspi_write_write(1, &cmd, 1, &new_reg_val);
}