mcu.h

#ifndef MCU_H_
#define MCU_H_

#define FE310_QSPI_BASE		0x10014000
#define FE310_PRCI_BASE		0x10008000

typedef struct {
	volatile unsigned long sckdiv;     // 0x00 Serial clock divisor
	volatile unsigned long sckmode;    // 0x04 Serial clock mode
	volatile unsigned long reserved0;  // 0x08 Reserved
	volatile unsigned long reserved1;  // 0x0C Reserved
	volatile unsigned long csid;       // 0x10 Chip select ID
	volatile unsigned long csdef;      // 0x14 Chip select default
	volatile unsigned long csmode;     // 0x18 Chip select mode
	volatile unsigned long reserved2;  // 0x1C Reserved
	volatile unsigned long reserved3;  // 0x20 Reserved
	volatile unsigned long reserved4;  // 0x24 Reserved
	volatile unsigned long delay0;     // 0x28 Delay control 0
	volatile unsigned long delay1;     // 0x2C Delay control 1
	volatile unsigned long reserved5;  // 0x30 Reserved
	volatile unsigned long reserved6;  // 0x34 Reserved
	volatile unsigned long reserved7;  // 0x38 Reserved
	volatile unsigned long reserved8;  // 0x3C Reserved
	volatile unsigned long fmt;        // 0x40 Frame format
	volatile unsigned long reserved9;  // 0x44 Reserved
	union {
		volatile unsigned long txdata;     // 0x48 Tx FIFO data
		volatile unsigned char txdatab[4];
	};
	union {
		volatile unsigned long rxdata;     // 0x4C Rx FIFO data
		volatile unsigned char rxdatab[4];
	};
	volatile unsigned long txmark;     // 0x50 Tx FIFO watermark
	volatile unsigned long rxmark;     // 0x54 Rx FIFO watermark
	volatile unsigned long reserved10; // 0x58 Reserved
	volatile unsigned long reserved11; // 0x5C Reserved
	volatile unsigned long fctrl;      // 0x60 SPI flash interface control
	volatile unsigned long ffmt;       // 0x64 SPI flash instruction format
	volatile unsigned long reserved12; // 0x68 Reserved
	volatile unsigned long reserved13; // 0x6C Reserved
	volatile unsigned long ie;         // 0x70 SPI interrupt enable
	volatile unsigned long ip;         // 0x74 SPI interrupt pending
} FE310_SPI;

typedef struct {
	volatile unsigned long hfrosccfg; // 0x00 Ring Oscillator Configuration and Status
	volatile unsigned long hfxosccfg; // 0x04 Crystal Oscillator Configuration and Status
	volatile unsigned long pllcfg;        // 0x08 PLL Configuration and Status
	volatile unsigned long plloutdiv;     // 0x0C PLL Final Divide Configuration
} FE310_PRCI;

typedef enum{
	QSPI_IP_TX_WATERMARK_MSK = 0x01,
	QSPI_IP_RX_WATERMARK_MSK = 0x02,
}QSPI_IP_WATERMARK;

typedef enum{
	QSPI_CSMODE_AUTO = 0,
	QSPI_CSMODE_HOLD = 2,
	QSPI_CSMODE_OFF = 3,
}QSPI_CSMODE;

typedef enum{
	QSPI_FMT_BUS_WIDTH_1 = 0,
	QSPI_FMT_BUS_WIDTH_2 = 1,
	QSPI_FMT_BUS_WIDTH_4 = 2,
	QSPI_FMT_BUS_WIDTH_MSK = 0x03,
}QSPI_FMT_BUS_WIDTH;

#endif /* MCU_H_ */