@@ -168,7 +168,7 @@ async def _execute_tou_switch_write(self, new_value: int):
         new_value &= 0x0FFF
         old_value = cache_get(self.hass, self, TOU_SWITCH_REGISTER)
         if old_value is not None:
-            old_value = int(old_value)
+            old_value = int(old_value) & 0x0FFF
         else:
             try:
                 old_value = await self._read_tou_switch_bitfield()
 
@@ -16,6 +16,8 @@
 from custom_components.solisconnect.sensor_data.cloud_mapping import (
     CLOUD_CID_MAP,
     CLOUD_INPUT_MAP,
+    TOU_SWITCH_CIDS_BY_BIT,
+    TOU_SWITCH_REGISTER,
     encode_cid_value,
     encode_engineering_value,
     registers_covered,
@@ -100,13 +102,18 @@ async def _update_cycle(self, now=None):
                 mapping = CLOUD_CID_MAP.get(cid)
                 if mapping is None:
                     continue  # the API returns extra related CIDs beyond those requested
+                if mapping.merge_register_bit is not None:
+                    continue  # TOU V2 switch bits are merged together below, not per-CID
                 words = encode_cid_value(mapping, msg)
                 if words:
-                    if mapping.merge_register_bit is not None:
-                        words = self._merge_bit_words(words, mapping.merge_register_bit)
                     self._publish_words(words)
                     cid_words += len(words)
 
+            switch_words = self._merge_switch_bits(batch)
+            if switch_words:
+                self._publish_words(switch_words)
+                cid_words += len(switch_words)
+
             controller.last_cloud_success = datetime.now(UTC)
             # INFO so it is visible in `ha core logs` when diagnosing live installs
             _LOGGER.info("Cloud poll complete: %s detail registers, %s cid registers", published, cid_words)
@@ -140,16 +147,37 @@ def _publish_words(self, words: dict[int, int]):
             cache_save(self.hass, self.controller, register, word)
             notify_register_update(self.hass, self.controller, register, word)
 
-    def _merge_bit_words(self, words: dict[int, int], bit_position: int) -> dict[int, int]:
-        """Merge one CID switch value into the shared TOU V2 bitfield register."""
-        register, bit_value = next(iter(words.items()))
-        current = cache_get(self.hass, self.controller, register)
-        merged = int(current) if current is not None else 0
-        if int(bit_value):
-            merged |= 1 << bit_position
+    def _merge_switch_bits(self, batch: dict[int, str]) -> dict[int, int] | None:
+        """Build the merged TOU V2 switch register from this poll's batch reads plus the cache.
+
+        A switch CID missing from one poll's batch response must not be treated as "off": on a
+        cold cache (nothing published yet) we only publish once every switch bit has been observed
+        at least once, so a transiently-missing CID can never permanently zero a bit it never
+        actually reported. On a warm cache, a missing CID simply leaves its bit as last observed.
+        """
+        observed: dict[int, int] = {}
+        for bit, cid in TOU_SWITCH_CIDS_BY_BIT.items():
+            msg = batch.get(cid)
+            if msg is None:
+                continue
+            words = encode_cid_value(CLOUD_CID_MAP[cid], msg)
+            if words:
+                observed[bit] = words[TOU_SWITCH_REGISTER]
+
+        current = cache_get(self.hass, self.controller, TOU_SWITCH_REGISTER)
+        if current is None:
+            if len(observed) < len(TOU_SWITCH_CIDS_BY_BIT):
+                return None  # incomplete cold-cache read; defer until a cycle observes every bit
+            merged = 0
         else:
-            merged &= ~(1 << bit_position)
-        return {register: merged}
+            merged = int(current)
+
+        for bit, value in observed.items():
+            if value:
+                merged |= 1 << bit
+            else:
+                merged &= ~(1 << bit)
+        return {TOU_SWITCH_REGISTER: merged}
 
     def _publish_status(self):
         """Pseudo-registers used by diagnostic derived sensors (same as DataRetrieval)."""
 
@@ -348,8 +348,14 @@ def _tou_v2_mappings() -> list[CloudCidMapping]:
 
 CLOUD_CID_MAP: dict[int, CloudCidMapping] = {m.cid: m for m in _CLOUD_CID_MAPPINGS}
 
-# Write routing: which CID a holding-register write lands on
-REGISTER_TO_CID: dict[int, CloudCidMapping] = {register: mapping for mapping in CLOUD_CID_MAP.values() for register in mapping.registers}
+# Write routing: which CID a holding-register write lands on. TOU V2 switch-slot mappings are
+# excluded here: all twelve of them share register 43707, so a plain dict comprehension would
+# silently collapse to whichever mapping iterates last. Writes to 43707 are handled by the
+# dedicated TOU_SWITCH_REGISTER special-case instead; any future caller that looks up 43707
+# here directly should get a clear miss rather than a wrong CID.
+REGISTER_TO_CID: dict[int, CloudCidMapping] = {
+    register: mapping for mapping in CLOUD_CID_MAP.values() if mapping.merge_register_bit is None for register in mapping.registers
+}
 TOU_SWITCH_REGISTER = 43707
 TOU_SWITCH_CIDS_BY_BIT: dict[int, int] = {
     mapping.merge_register_bit: mapping.cid for mapping in CLOUD_CID_MAP.values() if mapping.merge_register_bit is not None
 
@@ -40,7 +40,7 @@ The newer, richer scheduling mechanism with independent settings per slot.
   - `+2`: cut-off voltage (V, editable `number`, 0-300, ×0.1)
   - `+3..+6`: start hour, start minute, end hour, end minute (paired into a `time` entity)
 - SolisCloud mapping (`sensor_data/cloud_mapping.py`, `_tou_v2_mappings()`):
-  - Slot enable bits -> CIDs `5916-5927` (charge slots 1-6, then discharge slots 1-6), merged into the shared `43707` bitfield by `CloudDataRetrieval._merge_bit_words`.
+  - Slot enable bits -> CIDs `5916-5927` (charge slots 1-6, then discharge slots 1-6), merged into the shared `43707` bitfield by `CloudDataRetrieval._merge_switch_bits`. On a cold cache the merged register is only published once all 12 slot-switch CIDs have been observed in a poll cycle, so a CID transiently missing from one `atReadBatch` response is never mistaken for "off".
   - Target SOC -> CIDs `5928-5933` (charge), `5965, 5969, 5973, 5977, 5981, 5984` (discharge).
   - Battery current -> CIDs `5948-5963` family (charge), `5967-5986` family (discharge).
   - Cut-off voltage -> the paired CID in the same current/voltage CID families.
 
@@ -48,8 +48,20 @@
     636: "33",
     157: "52",
     158: "15",
+    # All 12 TOU V2 switch-slot CIDs must be present for the merged 43707 bitfield to publish
+    # on a cold cache (see CloudDataRetrieval._merge_switch_bits): a partial batch is treated
+    # as "unknown so far" rather than defaulting the unseen bits to off.
     5916: "1",
     5917: "0",
+    5918: "0",
+    5919: "0",
+    5920: "0",
+    5921: "0",
+    5922: "0",
+    5923: "0",
+    5924: "0",
+    5925: "0",
+    5926: "0",
     5927: "1",
     5946: "09:30-10:45",
     5948: "12.5",
 
@@ -8,8 +8,9 @@
 
 from custom_components.solisconnect.cloud.api_client import SolisCloudApiError
 from custom_components.solisconnect.cloud.cloud_controller import SolisCloudController
+from custom_components.solisconnect.cloud.cloud_retrieval import CloudDataRetrieval
 from custom_components.solisconnect.const import DOMAIN, VALUES
-from custom_components.solisconnect.sensor_data.cloud_mapping import CLOUD_CID_MAP, cid_msg_from_words
+from custom_components.solisconnect.sensor_data.cloud_mapping import CLOUD_CID_MAP, REGISTER_TO_CID, cid_msg_from_words
 
 SERIAL = "CLOUDSN1"
 
@@ -168,3 +169,43 @@ async def test_verify_tou_switch_mismatch_restores_device_truth(hass, controller
 
     assert controller.api.async_at_read_batch.await_count == 2
     assert hass.data[DOMAIN][VALUES][f"{SERIAL}|43707"] == 0b0001
+
+
+async def test_tou_switch_write_masks_stray_bits_in_cached_old_value(hass, controller):
+    """A corrupted/stray high bit in the cached bitfield must not leak into the API's old_value."""
+    hass.data[DOMAIN][VALUES][f"{SERIAL}|43707"] = 0x1003  # bits 0-1 set, plus a stray bit 12
+
+    with patch.object(controller.hass, "async_create_task", side_effect=_close_background_task):
+        await controller.async_write_holding_register(43707, 0b0101)
+
+    assert controller.api.async_control.await_args_list[0].kwargs["old_value"] == "3"
+
+
+def test_register_to_cid_excludes_tou_switch_register():
+    """All 12 TOU V2 switch mappings share register 43707; it must not resolve to any single CID."""
+    assert 43707 not in REGISTER_TO_CID
+
+
+class TestMergeSwitchBits:
+    """CloudDataRetrieval._merge_switch_bits: cold-cache-incomplete-batch handling for bug #10."""
+
+    @pytest.fixture
+    def retrieval(self, hass, controller):
+        hass.data[DOMAIN][VALUES] = {}
+        with patch.object(hass, "async_create_task", side_effect=_close_background_task):
+            return CloudDataRetrieval(hass=hass, controller=controller)
+
+    def test_cold_cache_incomplete_batch_defers_publish(self, retrieval):
+        """Only 3 of 12 switch CIDs observed and no prior cache: must not guess the other 9 bits are off."""
+        batch = {5916: "1", 5917: "0", 5927: "1"}
+        assert retrieval._merge_switch_bits(batch) is None
+
+    def test_cold_cache_complete_batch_publishes(self, retrieval):
+        batch = {cid: ("1" if cid in (5916, 5927) else "0") for cid in [5916, 5917, 5918, 5919, 5920, 5921, 5922, 5923, 5924, 5925, 5926, 5927]}
+        assert retrieval._merge_switch_bits(batch) == {43707: (1 << 0) | (1 << 11)}
+
+    def test_warm_cache_partial_batch_only_touches_observed_bits(self, hass, retrieval):
+        """With a warm cache, a CID missing from this poll's batch must leave its bit untouched."""
+        hass.data[DOMAIN][VALUES][f"{SERIAL}|43707"] = 0b0110  # bits 1 and 2 set
+        batch = {5916: "1"}  # only bit 0 observed this cycle
+        assert retrieval._merge_switch_bits(batch) == {43707: 0b0111}