Leave the hub's PSELF and RESET#/CDP pins open (#13)

Both pins are strap inputs sampled at power-up, and both were being driven to
the wrong state. Adafruit's CH334F breakout (product 5997) leaves each one
open; matching it fixes a bug that killed every restore through the dongle.

PSELF (18) was tied to GND, so the hub advertised bus-powered and its
downstream ports could only promise one unit load, 100 mA. Every Apple
restore-stage device asks for 500 mA:

  DFU          0x1227   unconfigured, but works -- DFU is endpoint-0 control
                        transfers only, which are legal in Address state
  Recovery     0x1281   configures
  MacBook Pro  0x12ac   kUSBFailedRequestedPower = 500, restore dies here

The last stage is the first that needs interfaces, and interfaces only exist
inside a configuration. Left open the pin floats high on its internal pull-up,
which is self-powered -- 500 mA per port, exactly the ask. The board still
draws from the host's VBUS; this is a declaration, not a supply, and nothing
draws the current either way (the target runs on its own battery and there is
no per-port VBUS switching).

RESET#/CDP (16) was held high by R5. That pin is also sampled at power-up:
high enables CDP, the downstream charging-port advertisement, and disables the
hub's low-power sleep. The datasheet wants it "completely suspended when not
reset". R5 is removed; the pin keeps its ~25k internal pull-up.

Fab package regenerated: 91 vias (was 93), 56 placements (was 57), 10k
quantity down to 2. DRC 0 violations, 0 unconnected.

Author: fcjr

docs/dongle/PRD.md

@@ -30,7 +30,10 @@ below.
 - Power the target from an external USB-C PD charger, up to 100 W (20 V / 5 A).
 - Source to the target whatever PD profile it asks for (5 V, 9 V, 15 V, 20 V,
   and ideally PPS ranges), subject to what the attached charger can supply.
-- Keep the dongle's own logic bus-powered from the host by default. The external
+- Keep the dongle's own logic bus-powered from the host by default. This is
+  about where power comes from, not what the USB hub declares — the hub's
+  PSELF pin is left open so it advertises self-powered, which is what allows
+  500 mA per downstream port (an Apple restore needs it). The external
   charger powers the target, not the dongle logic.
 - Keep the power subsystem optional to populate: an unpopulated board is
   electrically a Dongle Lite and must pass all Lite requirements.

hardware/dongle-lite/PRD.md

@@ -30,7 +30,11 @@ target's CC line. This mechanism is public and proven by the AsahiLinux
   on macOS, Windows, and Linux.
 - Present the target to the host as a normal DFU USB device so restorekit /
   Apple Configurator can restore it over USB 2.0.
-- Be bus-powered from the host port. No wall power required.
+- Be bus-powered from the host port. No wall power required. Note this is
+  about where the board draws power, not what the hub *declares*: U3's PSELF
+  pin is left open so the hub advertises self-powered, because that is what
+  lets its downstream ports promise the 500 mA an Apple restore asks for.
+  Strapping PSELF to GND to "match" being bus-powered breaks restores.
 - Expose the target's low-level serial console (AP/SEP UART over SBU) to the
   host as a second serial device, for debugging failed restores.
 - Be the smallest, cheapest board that does the above, and serve as the shared
@@ -206,7 +210,7 @@ assembly footprint at M1. Prefer JLCPCB Basic parts to cut loading fees.
 | Crystal + load caps | 12 MHz 3225 4-pin + 2x 22 pF | verify | RP2040 XOSC |
 | RP2040 USB series R | 22R x2 (0402) | Basic | on D+/D- up to the hub |
 | Boot button | SMD tactile 4P | Basic | RP2040 BOOTSEL |
-| USB 2.0 hub | CH334F (or FE1.1s) | C425949 (verify) | 1 upstream, 2 down |
+| USB 2.0 hub | CH334F | C5187527 | 1 upstream, 2 down (C425949 in an earlier draft was wrong — see BOM-sourcing.md) |
 | USB-C receptacle (Host + Target) | HRO TYPE-C-31-M-12 | C165948 | 16-pin, breaks out SBU + CC + D+/D- |
 | SBU level translators | 74AVC1T45GW | C282330 | 2x (1 per SBU line), per CS v3 |
 | 1.2 V rail | TLV70212 (1.2 V LDO) | C81462 | per CS v3.1 (divider is the older alt) |
@@ -253,6 +257,10 @@ assemble at JLCPCB. This is the highest-confidence source for the SBU block.
 | R1,R2,R5,R6 | 4.7k 0402 | C25900 | pullups |
 | R3, R4 | 10k 0402 | C25744 | |
 
+> **Superseded.** The table above is the early estimate, and its reference
+> designators do not match the built design. The authoritative BOM and
+> placement list are `mfg-jlcpcb-1s4l/bom.csv` and `cpl.csv`.
+
 Open BOM decisions:
 
 - The SBU block is now resolved to CS v3.1 parts (all JLCPCB-verified above);

hardware/dongle-lite/README.md

@@ -67,7 +67,7 @@ kicad-cli sch erc dongle-lite.kicad_sch
 |-----|------|------|----------|
 | U1 | RP2354A | C41378174 | MCU (USB-native composite; 2 MB internal flash) |
 | U2 | FUSB302BMPX | C132291 | USB-PD PHY, drives target CC (Apple DFU VDM) |
-| U3 | CH334F | C5187527 | USB 2.0 hub — host sees MCU + target |
+| U3 | CH334F | C5187527 | USB 2.0 hub — host sees MCU + target. `PSELF` (18) and `RESET#/CDP` (16) are left **open** — see below |
 | U5 | RT9013-33GB | C47773 | 3.3 V LDO from host 5 V |
 | U6 | TLV70212 | C81462 | 1.2 V LDO for the SBU translator low side |
 | U8, U9 | 74AVC1T45GW | C282330 | SBU1/SBU2 level translators (3.3 ↔ 1.2 V) |
@@ -78,6 +78,24 @@ kicad-cli sch erc dongle-lite.kicad_sch
 
 Full BOM/CPL for ordering are in the `mfg-jlcpcb*/` packages.
 
+### Hub strap pins
+
+`PSELF` (18) and `RESET#/CDP` (16) on U3 are both left open, matching Adafruit's
+CH334F breakout (product 5997).
+
+`PSELF` has a built-in pull-up and defaults high = **self-powered**, which is
+what makes the hub advertise 500 mA per downstream port. Tied to GND it
+advertises bus-powered and caps every port at one unit load, 100 mA. A target
+Mac in DFU fits under that, but every later restore stage asks for 500 mA, so
+the host refuses to configure the target and the restore dies partway through
+with a power error. The board still draws from the host's VBUS — this is a
+declaration, not a supply.
+
+`RESET#/CDP` is sampled at power-up too: held high it enables CDP (downstream
+charging-port advertisement) and turns off the hub's low-power sleep. The
+datasheet wants it "completely suspended when not reset", so there is no
+pull-up on it.
+
 ## ERC configuration
 
 `pin_not_driven`, `pin_to_pin`, `lib_symbol_issues`, and `lib_symbol_mismatch`

hardware/dongle-lite/case/README.md

@@ -11,9 +11,10 @@ uv run case.py
 
 writes `output/`:
 
-- `dongle-lite-case.step` — assembly (bottom + lid in place)
+- `dongle-lite-case.step` — assembly (bottom + lid + inlay in place)
 - `bottom.stl` — tray, prints as-is
 - `lid.stl` — already flipped flat-side-down for printing
+- `lid-inlay.stl` — the white text inlay, same orientation as `lid.stl`
 
 ## Design
 
@@ -24,16 +25,43 @@ writes `output/`:
 - Port bays: the receptacle sits flush with the board edge, 1.8 mm behind
   the outer face, so the end wall has to clear the cable's overmold, not
   just the plug shell — otherwise the plug stops ~2 mm short of seating.
-  Each end is open 12.6 x 6.2 mm (flared to 14 mm over the outer 0.8 mm for
-  a lead-in), which takes an overmold up to about 12 x 5.8 mm. The bay runs
-  from the cavity floor up, so there's no thin ledge and nothing to bridge.
+  Each end is open 15.0 x 6.8 mm all the way through, with an 18.6 mm
+  rounded relief pocket 1.0 mm into the outer face for a chunky overmold to
+  nose into. That takes an overmold up to about 14.6 x 6.3 mm, or 16 mm
+  wide at the mouth. The bay is open to the top of the tray, so there's
+  nothing to bridge.
+
+  The top is the binding constraint, not the sides: the board sits on the
+  floor, which puts the connector centre 4.83 mm off the bottom of an
+  8.8 mm case, leaving 0.8 mm of lid above the bay and 1.2 mm of floor
+  below. `PORT_Z1` is what buys taller overmolds, at the cost of that roof.
 - Openings: 1.8 mm LED windows over D1 (PWR) and D2 (STAT), 2.4 mm
   paperclip hole over the BOOT button.
 - Engraving: bold, 0.6 mm deep with flat bottoms, all reading across the
   width. HOST / TARGET with arrows at the port ends, wordmark centered in
   the clear band above the LEDs, and STAT / PWR / BOOT right-aligned beside
-  their own holes. The lid prints top-face-down, so a filament swap at
-  0.6 mm gives two-color inlaid text.
+  their own holes.
+
+## White text inlay
+
+`lid-inlay.stl` is exactly the volume of the engraved pockets, exported in
+the same orientation and position as `lid.stl` — union the two and you get
+a flat-topped lid, with no interference and no gap.
+
+With a multi-material printer (MMU / AMS / toolchanger): load `lid.stl`,
+add `lid-inlay.stl` to it as a second *part* of the same object (not a
+separate object, so it isn't re-centred), assign white to the inlay, print
+the lid top-face-down. The text comes out flush and white.
+
+Single extruder, no MMU: print `lid-inlay.stl` on its own in white, 0.6 mm
+of flat letters, and glue them in. Fiddly on the small labels.
+
+What does *not* work is a plain filament swap. The lid prints top-face-down
+and the text is recessed, so the letters are voids in the first three
+layers: swapping at 0.6 mm colours the top face and leaves the letters in
+the body colour — the inverse of what you want. Getting white letters out
+of one extruder would mean embossing the text proud of the lid instead of
+engraving it, which trades the flush finish for something that scuffs.
 - Outer size: 26.2 x 81.2 x 8.8 mm, 1.8 mm walls.
 
 The lid graphics are built in absolute coordinates and cut in a single

hardware/dongle-lite/case/case.py

@@ -45,12 +45,19 @@
 # outer face, so a plug can only seat if the end wall is fully open in front
 # of it -- a plain shell-sized notch would leave the cable's overmold hitting
 # the case ~2 mm short. The bay is sized for the overmold instead of the
-# shell and runs from the cavity floor up, so there is no thin ledge to print.
-PORT_W = 12.6
-PORT_Z0 = 0.0  # flush with the cavity floor
-PORT_Z1 = 6.2  # leaves 1.0 mm of lid above the bay
-PORT_FLARE = 0.7  # sideways lead-in over the outer 0.8 mm
-PORT_FLARE_D = 0.8
+# shell, and a shallow recess around it in the outer face gives a chunky
+# overmold somewhere to nose into.
+#
+# The top is the binding constraint, not the sides: the board sits on the
+# floor, so the connector centre is 4.83 mm off the bottom of an 8.8 mm case
+# and there is only ~1 mm of lid left above the bay. Raising PORT_Z1 further
+# is what buys taller overmolds, at the cost of that roof.
+PORT_W = 15.0
+PORT_Z0 = -0.4  # 0.4 below the cavity floor, leaving 1.2 mm of tray floor
+PORT_Z1 = 6.4  # leaves 0.8 mm of lid above the bay
+PORT_RECESS_W = 18.6  # relief pocket in the outer face, around the bay
+PORT_RECESS_D = 1.0  # of the 1.8 mm wall
+PORT_RECESS_R = 1.2
 
 LIP_T = 1.2
 LIP_H = 1.6
@@ -78,30 +85,25 @@ def outer_profile(height, z0):
 
 
 def port_cutter(sign):
-    """Plug bay through one end wall, flared for a lead-in on the outer face.
+    """Plug bay through one end wall, plus its relief pocket.
 
     Built with the plug axis along +Z (z = 0 at the outer face, +Z inward)
-    then rotated onto +/-Y, so the loft never has to be built on a tilted
-    workplane.
+    then rotated onto +/-Y, so the rounded pocket never has to be filleted on
+    a tilted workplane -- that is what crashes OCC's cleanup.
     """
     h = PORT_Z1 - PORT_Z0
-    bay = (
-        cq.Workplane("XY")
-        .box(PORT_W, h, 3.0, centered=(True, True, False))
-        .union(
-            cq.Workplane("XY")
-            .rect(PORT_W + 2 * PORT_FLARE, h)
-            .workplane(offset=PORT_FLARE_D)
-            .rect(PORT_W, h)
-            .loft()
-        )
-        .union(
-            cq.Workplane("XY", origin=(0, 0, -1.0))
-            .box(PORT_W + 2 * PORT_FLARE, h, 1.0, centered=(True, True, False))
-        )
+    bay = cq.Workplane("XY", origin=(0, 0, -1.5)).box(
+        PORT_W, h, 4.5, centered=(True, True, False)
+    )
+    recess = (
+        cq.Workplane("XY", origin=(0, 0, -1.5))
+        .box(PORT_RECESS_W, h, 1.5 + PORT_RECESS_D, centered=(True, True, False))
+        .edges("|Z")
+        .fillet(PORT_RECESS_R)
     )
     return (
-        bay.val()
+        bay.union(recess, clean=False)
+        .val()
         .rotate((0, 0, 0), (1, 0, 0), sign * 90)
         .translate((0, sign * OUT_L / 2, (PORT_Z0 + PORT_Z1) / 2))
     )
@@ -208,7 +210,10 @@ def thru_hole(x, y, d):
     )
 
 
-marks = engrave("restorekit", 0, WORDMARK_Y, WORDMARK_SIZE)
+# The graphics are kept separate from the holes: they are both the pockets
+# cut into the lid and, exported on their own, the white inlay that drops
+# back into them.
+inlay = engrave("restorekit", 0, WORDMARK_Y, WORDMARK_SIZE)
 for m in (
     engrave("HOST", 0, PORT_LABEL_Y, PORT_LABEL_SIZE),
     engrave("TARGET", 0, -PORT_LABEL_Y, PORT_LABEL_SIZE),
@@ -217,11 +222,16 @@ def thru_hole(x, y, d):
     engrave("STAT", PIN_LABEL_RIGHT, LED2[1], PIN_LABEL_SIZE, halign="right"),
     engrave("PWR", PIN_LABEL_RIGHT, LED1[1], PIN_LABEL_SIZE, halign="right"),
     engrave("BOOT", PIN_LABEL_RIGHT, SW1[1], PIN_LABEL_SIZE, halign="right"),
+):
+    inlay = inlay.union(m)
+
+marks = inlay
+for h in (
     thru_hole(*LED1, 1.8),   # PWR window
     thru_hole(*LED2, 1.8),   # STAT window
     thru_hole(*SW1, 2.4),    # BOOT, paperclip
 ):
-    marks = marks.union(m)
+    marks = marks.union(h)
 lid = lid.cut(marks, clean=False)
 
 # --- export ---
@@ -232,13 +242,17 @@ def thru_hole(x, y, d):
     cq.Assembly()
     .add(bottom, name="bottom", color=cq.Color(0.25, 0.25, 0.28))
     .add(lid, name="lid", color=cq.Color(0.85, 0.85, 0.87))
+    .add(inlay, name="inlay", color=cq.Color(1.0, 1.0, 1.0))
 )
 assembly.export(os.path.join(out, "dongle-lite-case.step"))
 
 cq.exporters.export(bottom, os.path.join(out, "bottom.stl"))
-# flip the lid so its flat top sits on the print bed
-lid_print = lid.rotate((0, 0, 0), (0, 1, 0), 180)
-cq.exporters.export(lid_print, os.path.join(out, "lid.stl"))
+# flip the lid so its flat top sits on the print bed. The inlay gets the same
+# transform, so loading it as a second part lands it in its pockets with no
+# repositioning.
+flip = lambda w: w.rotate((0, 0, 0), (0, 1, 0), 180)
+cq.exporters.export(flip(lid), os.path.join(out, "lid.stl"))
+cq.exporters.export(flip(inlay), os.path.join(out, "lid-inlay.stl"))
 
 print("wrote", out)
 print(f"outer: {OUT_W} x {OUT_L} x {OUT_H} mm")