Von Neumann Pipelined Processor

A robust 32-bit 5-stage pipelined processor implementation in VHDL, featuring advanced architectural components such as hazard detection, forwarding, and interrupt handling.

📖 Overview

This project implements a Von Neumann architecture processor with a 5-stage pipeline:

1. Fetch (IF)
2. Decode (ID)
3. Execute (EX)
4. Memory (MEM)
5. Write Back (WB)

The design handles various dependencies and hazards to ensure correct execution flow, supporting a rich instruction set including arithmetic, logical, memory, branching, and stack operations.

✨ Features

• 5-Stage Pipeline: Parallel instruction processing for improved throughput.
• Hazard Detection Unit: Automatically detects and resolves data and control hazards (e.g., stalling, flushing).
• Forwarding Unit: Implements data forwarding (bypassing) to minimize pipeline stalls.
• Stack Support: Dedicated Stack Pointer (SP) with PUSH/POP/CALL/RET instructions.
• Branching: Conditional (JZ, JN, JC) and unconditional jumps, including Call/Return mechanisms.

🏗️ Architecture

The following diagram illustrates the high-level design and data flow of the processor:

(Click here for a high-quality view)

📂 Project Structure

• Processor.vhd: Top-level entity connecting all stages and components.
• Processor.py: Python script to automate ModelSim simulation setup.
• components/: Core units (ALU, Register File, Control Unit, Hazard Unit, Forwarding Unit, etc.).
• components/Pipelined_Registers/: Pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB) to pass data between stages.
• stages/: VHDL files for each pipeline stage (Fetch, Decode, Execute, Memory, WriteBack).
• simulate/: Generated directory for ModelSim project files (created by the Python script).
• test/: Testbench files and DO scripts.
• docs/: Documentation and design assets.

🚀 Getting Started

Prerequisites

• ModelSim (or compatible VHDL simulator).
• Python 3.x (optional, for using the automation script).

✍️ Writing and Assembling Code

The processor executes machine code stored in a memory file. You can write assembly code and use the provided assembler to generate this file.

1. Write Assembly: Edit or create your assembly code in test/program.asm.
2. Assemble: Run the assembler script to convert your assembly into a binary memory file:

   python test/assembler.py

   This generates test/instruction.mem.
3. Simulation Input: The Processor.py script and the VHDL memory component are configured to read from instruction.mem.

🚀 Running the Simulation

Option 1: Using the Python Automation Script (Recommended)

The Processor.py script automates the entire process: creating the project, copying memory files, and launching ModelSim.

1. Configuration: Open Processor.py and ensure the repoPath and modelsim_exe paths match your local installation.
2. Run:

   python Processor.py

   This script will take test/instruction.mem, move it to the simulation directory, compile all VHDL files, and start the simulation.

Option 2: Manual ModelSim Setup

1. Open ModelSim and create a new project.
2. Add all VHDL files from components/, stages/, and the root Processor.vhd.
3. Place a copy of instruction.mem in your ModelSim project directory.
4. Compile all files and load the Processor entity.
5. Run the simulation (optionally using a .do file from test/do/).

📜 Opcode Reference

For a detailed list of supported instructions and their binary codes, please refer to the Opcode Reference.