Merge pull request #5 from gerph/fix-disassembly-accessor-reads

Fix live-register access after accessor refactor

Author: gerph

riscos_disassemble/arm/disassemble.py

@@ -357,7 +357,7 @@ def psr_name(self, psr, mask):
 
         # Logic taken from BTSDump/arm.c
         if psr is None:
-            psr = self.get_pstate()
+            psr = self.access.get_pstate()
         is26bit = (psr & (1<<4)) == 0
         mode = psr & 15
         mode_name = self.psr_modes[mode]
@@ -482,19 +482,19 @@ def _operand_registers(self, operand, shift=None, maybe_presentable=False):
         if operand.type == self._const.ARM_OP_REG:
             regnum = self.inv_reg_map.get(operand.reg, None)
             if regnum is not None:
-                accumulator.append('R%i = &%08x' % (regnum, self.get_reg(regnum)))
+                accumulator.append('R%i = &%08x' % (regnum, self.access.get_reg(regnum)))
         if operand.type == self._const.ARM_OP_MEM:
             # Base
             base = None
             regnum = self.inv_reg_map.get(operand.mem.base, None)
             if regnum is not None:
-                base = self.get_reg(regnum)
+                base = self.access.get_reg(regnum)
                 accumulator.append('R%i = &%08x' % (regnum, base))
 
             # Index
             regnum = self.inv_reg_map.get(operand.mem.index, None)
             if regnum is not None:
-                accumulator.append('R%i = &%08x' % (regnum, self.get_reg(regnum)))
+                accumulator.append('R%i = &%08x' % (regnum, self.access.get_reg(regnum)))
             else:
                 # There's no index, so we'll check if there's a presentable value string at that position
                 if base is not None and maybe_presentable and self.config.show_referenced_pointers:
@@ -514,7 +514,7 @@ def _operand_registers(self, operand, shift=None, maybe_presentable=False):
                 # This is a shift by a register, so we can include its value in the result
                 regnum = self.inv_reg_map.get(operand.shift.value, None)
                 if regnum is not None:
-                    accumulator.append('R%i = &%08x' % (regnum, self.get_reg(regnum)))
+                    accumulator.append('R%i = &%08x' % (regnum, self.access.get_reg(regnum)))
 
         return accumulator
 
@@ -875,7 +875,7 @@ def disassemble_instruction(self, address, inst,
                 if swic in (0x6f, 0x71):
                     rn = 10 if swi & 255 == 0x6f else 12
                     if live_registers:
-                        real_swi = self.get_reg(rn)
+                        real_swi = self.access.get_reg(rn)
                         comment = 'R%s = &%x' % (rn, real_swi)
                         callaswi_name = self.access.decode_swi(real_swi)
                         if callaswi_name:
@@ -976,7 +976,7 @@ def disassemble_instruction(self, address, inst,
                     regnum = self.inv_reg_map.get(i.operands[2].reg, None)
                     if regnum is not None:
                         if live_registers:
-                            comment = 'Table dispatch index #%s' % (self.get_reg(regnum),)
+                            comment = 'Table dispatch index #%s' % (self.access.get_reg(regnum),)
                         else:
                             comment = 'Table dispatch index R%s' % (regnum,)
                 else:

riscos_disassemble/arm64/disassemble.py

@@ -377,7 +377,7 @@ def _capstone_reg_assignment(self, regmap):
         @return: String describing its current value
         """
         regnum = regmap[1]
-        value = self.get_reg(regnum & 31)
+        value = self.access.get_reg(regnum & 31)
         value = value & regmap[2]
         return "%s = %s" % (regmap[0], self._value_description(value))
 
@@ -390,7 +390,7 @@ def _capstone_reg_value(self, regmap):
         @return: Value of the register
         """
         regnum = regmap[1]
-        value = self.get_reg(regnum & 31)
+        value = self.access.get_reg(regnum & 31)
         value = value & regmap[2]
         return value
 
@@ -500,7 +500,7 @@ def disassemble_instruction(self, address, inst,
                         # This is a RISC OS system SWI
 
                         # Look up the SWI number, if we can.
-                        swi = self.get_reg(10)
+                        swi = self.access.get_reg(10)
 
                         # Special cases for some SWIs
                         swic = swi & ~0x20000
@@ -517,7 +517,7 @@ def disassemble_instruction(self, address, inst,
                         elif swic == 2:
                             # OS_Write0
                             if live_memory and live_registers:
-                                r0 = self.get_reg(0)
+                                r0 = self.access.get_reg(0)
                                 string = self.access.get_memory_string(r0)
                                 if string:
                                     string = "\"%s\"" % (string.decode('latin-1').encode('ascii', 'backslashreplace'),)