@@ -72,7 +72,7 @@ if(NOT GPU_BACKEND STREQUAL "ROCM")
7272 else ()
7373 # Best-effort probe of the visible GPU (mirrors build.sh detect_with_torch).
7474 execute_process (
75- COMMAND "${Python_EXECUTABLE} " -c "import torch; assert torch.cuda.is_available(); mj, mn = torch.cuda.get_device_capability(0); print(f'{mj}.{mn}a' if (mj, mn) in ((9, 0), (12, 0)) else f'{mj}.{mn}')"
75+ COMMAND "${Python_EXECUTABLE} " -c "import torch; assert torch.cuda.is_available(); mj, mn = torch.cuda.get_device_capability(0); print(f'{mj}.{mn}a' if (mj, mn) in ((9, 0), (12, 0), (12, 1) ) else f'{mj}.{mn}')"
7676 OUTPUT_VARIABLE _FV_ARCH_LIST
7777 OUTPUT_STRIP_TRAILING_WHITESPACE
7878 RESULT_VARIABLE _fv_detect_rc
@@ -209,7 +209,7 @@ else()
209209 elseif (FASTVIDEO_KERNEL_BUILD_ATTN_QAT_INFER STREQUAL "AUTO" )
210210 if (TORCH_CUDA_ARCH_LIST)
211211 string (REGEX MATCH
212- "(^|[; ,])((12\\ .0a)|(120a)|(sm_120a))([; ,]|$)"
212+ "(^|[; ,])((12\\ .0a)|(120a)|(sm_120a)|(12 \\ .1a)|(121a)|(sm_121a) )([; ,]|$)"
213213 _HAS_120A "${TORCH_CUDA_ARCH_LIST} " )
214214 if (_HAS_120A)
215215 set (_WANTS_ATTN_QAT_INFER ON )
@@ -253,14 +253,16 @@ set(BUILD_CXX_KERNELS ON)
253253# ---------------------------------------------------------------------------
254254# Per-arch split for the Blackwell FP4 (attn_qat_infer) build
255255# ---------------------------------------------------------------------------
256- # The FP4 kernels are sm_120a-only (they emit `cvt.e2m1x2` etc.), while the main
257- # extension (Hopper-only TK + generic turbodiffusion) targets the full arch list.
256+ # The FP4 kernels are Blackwell-only (sm_120a, plus sm_121a on CUDA >= 12.9; they
257+ # emit `cvt.e2m1x2` etc.), while the main extension (Hopper-only TK + generic
258+ # turbodiffusion) targets the full arch list.
258259# find_package(Torch) injects ONE global -gencode list into CMAKE_CUDA_FLAGS that
259260# forces every target onto every arch, so the FP4 sources also get the sm_90a pass
260261# and ptxas rejects their Blackwell instructions. Strip that global list and drive
261- # arch per target via CUDA_ARCHITECTURES instead (the fp4* targets pin 120a below;
262- # the main extension gets the full list). Only do this for the FP4 build with an
263- # explicit arch list, so the cu126 / local autodetect paths stay untouched.
262+ # arch per target via CUDA_ARCHITECTURES instead (the fp4* targets pin their arch
263+ # below via _fv_fp4_archs; the main extension gets the full list). Only do this for
264+ # the FP4 build with an explicit arch list, so the cu126 / local autodetect paths
265+ # stay untouched.
264266if (ENABLE_ATTN_QAT_INFER AND TORCH_CUDA_ARCH_LIST)
265267 message (STATUS "[per-arch] CMAKE_CUDA_FLAGS before strip: ${CMAKE_CUDA_FLAGS} " )
266268 string (REGEX REPLACE "-gencode[ =]+arch=[^ ]+" "" CMAKE_CUDA_FLAGS "${CMAKE_CUDA_FLAGS} " )
@@ -270,7 +272,7 @@ if(ENABLE_ATTN_QAT_INFER AND TORCH_CUDA_ARCH_LIST)
270272 set (FASTVIDEO_MAIN_CUDA_ARCHS "${TORCH_CUDA_ARCH_LIST} " )
271273 string (REPLACE "sm_" "" FASTVIDEO_MAIN_CUDA_ARCHS "${FASTVIDEO_MAIN_CUDA_ARCHS} " )
272274 string (REPLACE "." "" FASTVIDEO_MAIN_CUDA_ARCHS "${FASTVIDEO_MAIN_CUDA_ARCHS} " )
273- message (STATUS "[per-arch] main extension archs=${FASTVIDEO_MAIN_CUDA_ARCHS} , fp4* archs=120a " )
275+ message (STATUS "[per-arch] main extension archs=${FASTVIDEO_MAIN_CUDA_ARCHS} " )
274276endif ()
275277
276278# Compiler flags
@@ -401,6 +403,15 @@ if(ENABLE_ATTN_QAT_INFER)
401403 "-DDQINRMEM"
402404 )
403405
406+ # The FP4 kernels are arch-conditional (sm_120a). Add sm_121a (GB10 / DGX
407+ # Spark) only when the toolkit knows it -- compute_121 first exists in CUDA
408+ # 12.9, so unconditionally adding it would break sm_120a builds on CUDA 12.8.
409+ set (_fv_fp4_archs "120a" )
410+ if (NOT CUDAToolkit_VERSION VERSION_LESS 12.9)
411+ list (APPEND _fv_fp4_archs "121a" )
412+ endif ()
413+ message (STATUS "[per-arch] fp4* archs=${_fv_fp4_archs} (CUDAToolkit ${CUDAToolkit_VERSION} )" )
414+
404415 Python_add_library (fp4attn_cuda MODULE WITH_SOABI
405416 attn_qat_infer/blackwell/api.cu
406417 )
@@ -411,7 +422,7 @@ if(ENABLE_ATTN_QAT_INFER)
411422 $<$<COMPILE_LANGUAGE :CUDA >:${ATTN_QAT_INFER_CUDA_FLAGS} >
412423 )
413424 set_target_properties (fp4attn_cuda PROPERTIES
414- CUDA_ARCHITECTURES "120a "
425+ CUDA_ARCHITECTURES "${_fv_fp4_archs} "
415426 CXX_STANDARD 17
416427 CUDA_STANDARD 17
417428 )
@@ -427,7 +438,7 @@ if(ENABLE_ATTN_QAT_INFER)
427438 $<$<COMPILE_LANGUAGE :CUDA >:${ATTN_QAT_INFER_CUDA_FLAGS} >
428439 )
429440 set_target_properties (fp4quant_cuda PROPERTIES
430- CUDA_ARCHITECTURES "120a "
441+ CUDA_ARCHITECTURES "${_fv_fp4_archs} "
431442 CXX_STANDARD 17
432443 CUDA_STANDARD 17
433444 )
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