Commit 38412b2
[perf]: fuse the MiniMax H3 VSA gate combine, accumulate in place at inference
torch.addcmul keeps one full-sequence temporary under grad instead of two,
and when the sparse output is not tracked by autograd the gate branch
accumulates into it directly, allocating nothing. The product is no longer
rounded to bf16 before the add, so gated values move by at most half a bf16
ulp (towards the fp32 value). test_vsa_h3_backward.py passes on the Triton
and FA4 CuTe backends on a GB200.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01NjFimeedTQWxgqSzP5xo4j1 parent 28c68b9 commit 38412b2
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