Media Engine: consolidate IsMeSensitiveHwPage to MemMapFunctions.cpp

Move the ME hardware page check function from three separate static copies
(ARM64 backend, x64 backend, IRPassSimplify) into a single implementation
in MemMapFunctions.cpp with declaration in MemMap.h.

All three consumers (NeedsGenericMeHwAccess in both JIT backends and
ApplyMeMemoryValidation in the IR pass) now use Memory::IsMeSensitiveHwPage().

Author: frangarcj

Core/MIPS/ARM64/Arm64IRCompLoadStore.cpp

@@ -38,27 +38,6 @@ namespace MIPSComp {
 using namespace Arm64Gen;
 using namespace Arm64IRJitConstants;
 
-// Returns true if the given address falls within an ME-sensitive hardware register page.
-// These are pages where ME code reads/writes MMIO registers that need to go through
-// ReadFromHardware/WriteToHardware rather than direct memory access.
-//
-// Physical ranges (after masking with 0x1FFFFFFF):
-//   0x1C000000 - System Controller (power, clock, reset control)
-//   0x1C100000 - ME interrupt / soft-interrupt registers (0xBC100044, 0xBC100048, etc.)
-//   0x1C200000 - ME/SC communication registers
-//   0x1C300000 - Additional system control
-//   0x1CC00000 - VME (Video ME) registers (CSC, etc.)
-//   0x1D000000 - DMACplus registers
-static bool IsMeSensitiveHwPage(u32 address) {
-	u32 phys = address & 0x1FFFFFFF;
-	return (phys >= 0x1C000000 && phys < 0x1C001000) ||
-		(phys >= 0x1C100000 && phys < 0x1C101000) ||
-		(phys >= 0x1C200000 && phys < 0x1C201000) ||
-		(phys >= 0x1C300000 && phys < 0x1C301000) ||
-		(phys >= 0x1CC00000 && phys < 0x1CC01000) ||
-		(phys >= 0x1D000000 && phys < 0x1D001000);
-}
-
 static u32 ComputeConstantAddress(const IRInst &inst, Arm64IRRegCache &regs) {
 	uint64_t base = 0;
 	if (inst.src1 != MIPS_REG_ZERO) {
@@ -83,7 +62,7 @@ static bool NeedsGenericMeHwAccess(const IRInst &inst, Arm64IRRegCache &regs, co
 		return false;
 	}
 	u32 addr = ComputeConstantAddress(inst, regs);
-	bool sensitive = IsMeSensitiveHwPage(addr);
+	bool sensitive = Memory::IsMeSensitiveHwPage(addr);
 	if (sensitive) {
 		DEBUG_LOG(Log::JIT, "ME HW access detected: addr=%08x src1=%d constant=%08x -> GENERIC", addr, inst.src1, inst.constant);
 	}

Core/MIPS/IR/IRPassSimplify.cpp

@@ -6,6 +6,7 @@
 #include "Common/Data/Convert/SmallDataConvert.h"
 #include "Common/Log.h"
 #include "Core/Config.h"
+#include "Core/MemMap.h"
 #include "Core/MIPS/MIPSVFPUUtils.h"
 #include "Core/MIPS/IR/IRAnalysis.h"
 #include "Core/MIPS/IR/IRInterpreter.h"
@@ -1808,12 +1809,6 @@ static IRMemoryOpInfo IROpMemoryAccessSize(IROp op) {
 	}
 }
 
-// Matches IsMeSensitiveHwPage() in Arm64IRCompLoadStore.cpp.
-static bool IsMeHwPageForValidation(u32 address) {
-	u32 phys = address & 0x1FFFFFFF;
-	return (phys >= 0x1C000000 && phys < 0x1D100000);
-}
-
 bool ApplyMeMemoryValidation(const IRWriter &in, IRWriter &out, const IROptions &opts) {
 	CONDITIONAL_DISABLE;
 	if (g_Config.bFastMemory)
@@ -1833,7 +1828,7 @@ bool ApplyMeMemoryValidation(const IRWriter &in, IRWriter &out, const IROptions
 			} else {
 				// src1 == ZERO, address is fully constant.
 				u32 addr = inst.constant;
-				if (IsMeHwPageForValidation(addr)) {
+				if (Memory::IsMeSensitiveHwPage(addr)) {
 					// The backend handles ME HW registers.
 					skipValidation = true;
 				}

Core/MIPS/x86/X64IRCompLoadStore.cpp

@@ -37,17 +37,6 @@ namespace MIPSComp {
 using namespace Gen;
 using namespace X64IRJitConstants;
 
-// See Arm64IRCompLoadStore.cpp for detailed documentation of these ranges.
-static bool IsMeSensitiveHwPage(u32 address) {
-	u32 phys = address & 0x1FFFFFFF;
-	return (phys >= 0x1C000000 && phys < 0x1C001000) ||
-		(phys >= 0x1C100000 && phys < 0x1C101000) ||
-		(phys >= 0x1C200000 && phys < 0x1C201000) ||
-		(phys >= 0x1C300000 && phys < 0x1C301000) ||
-		(phys >= 0x1CC00000 && phys < 0x1CC01000) ||
-		(phys >= 0x1D000000 && phys < 0x1D001000);
-}
-
 static u32 ComputeConstantAddress(const IRInst &inst, X64IRRegCache &regs) {
 	uint64_t base = 0;
 	if (inst.src1 != MIPS_REG_ZERO) {
@@ -68,7 +57,7 @@ static bool NeedsGenericMeHwAccess(const IRInst &inst, X64IRRegCache &regs, cons
 		return false;
 	if (inst.src1 != MIPS_REG_ZERO && !regs.IsGPRImm(inst.src1))
 		return false;
-	return IsMeSensitiveHwPage(ComputeConstantAddress(inst, regs));
+	return Memory::IsMeSensitiveHwPage(ComputeConstantAddress(inst, regs));
 }
 
 Gen::OpArg X64JitBackend::PrepareSrc1Address(IRInst inst) {

Core/MemMap.h

@@ -336,6 +336,11 @@ inline bool IsValid4AlignedAddress(const u32 address) {
 	}
 }
 
+// Returns true if address is in an ME-sensitive hardware register page
+// (system controller, ME interrupts, VME, DMACplus, etc.).
+// Implementation in MemMapFunctions.cpp.
+bool IsMeSensitiveHwPage(u32 address);
+
 inline u32 MaxSizeAtAddress(const u32 address){
 	if ((address & 0x3E000000) == 0x08000000) {
 		return 0x08000000 + g_MemorySize - (address & 0x3FFFFFFF);

Core/MemMapFunctions.cpp

@@ -171,6 +171,27 @@ static inline bool IsMeHwRegister(u32 address) {
 	return (phys >= 0x1C000000 && phys < 0x1D100000);
 }
 
+// Finer-grained check for specific ME hardware register pages.
+// Used by IR backends and validation passes to detect MMIO accesses
+// that must go through ReadFromHardware/WriteToHardware.
+//
+// Physical ranges (after masking with 0x1FFFFFFF):
+//   0x1C000000 - System Controller (power, clock, reset control)
+//   0x1C100000 - ME interrupt / soft-interrupt registers (0xBC100044, 0xBC100048, etc.)
+//   0x1C200000 - ME/SC communication registers
+//   0x1C300000 - Additional system control
+//   0x1CC00000 - VME (Video ME) registers (CSC, etc.)
+//   0x1D000000 - DMACplus registers
+bool IsMeSensitiveHwPage(u32 address) {
+	u32 phys = address & 0x1FFFFFFF;
+	return (phys >= 0x1C000000 && phys < 0x1C001000) ||
+		(phys >= 0x1C100000 && phys < 0x1C101000) ||
+		(phys >= 0x1C200000 && phys < 0x1C201000) ||
+		(phys >= 0x1C300000 && phys < 0x1C301000) ||
+		(phys >= 0x1CC00000 && phys < 0x1CC01000) ||
+		(phys >= 0x1D000000 && phys < 0x1D001000);
+}
+
 // The page at 0xBC100000 (physical 0x1C100000) is mapped in the arena.
 // The JIT does raw LDR/STR there, and the interpreter goes through these
 // helpers.  Per-CPU mutex masking is NOT applied because the emulator is