TMA_Metrics-full.csv

TMA,Version,5.2-full,Intel,,,5.200-full,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,5.2000-full,,,full,full,full;bot;,full,full,full,full
.,,,Confidential,,,,,,Server,,Server,Server,Server,,,,Server,,Server,Server,,Server,,Server,,Server,,Server,,Server,,,,,,,,,,,;bot;EDP;perf,,,,
Key,Level1,Level2,Level3,Level4,Level5,Level6,PTL,LNL/ARL,GNR,MTL,EMR,SPR-HBM,SPR,ADL/RPL,TGL,RKL,ICX,ICL,CPX,CLX,KBLR/CFL/CML,SKX,SKL/KBL,BDX,BDW,HSX,HSW,IVT,IVB,JKT/SNB-EP,SNB,Locate-with,Count Domain,Metric Description,Threshold,Version,Metric Group,Metric Max,flavor,level,Tool;bot;,ToolAlias,Attribute,Tuning Hint,Link
Bottleneck,Mispredictions,,,,,,,,,,,,,,,,,,,,,,100 * ( 1 - #Umisp ) * ( Branch_Mispredicts + Fetch_Latency * Mispredicts_Resteers / ##Fetch_Latency ),,,,,,,,,,Scaled_Slots,Total pipeline cost of Branch Misprediction related bottlenecks,> 20; $issueBM,4.7,Bad;BadSpec;BrMispredicts;BvMP,,pub/v4.3,0,;bot;EDP;perf,,InTree,,
Bottleneck,Big_Code,,,,,,,,,,,,,,,,,,,,,,100 * Fetch_Latency * ( ITLB_Misses + ICache_Misses + Unknown_Branches ) / ##Fetch_Latency,,,,,,,,,,Scaled_Slots,Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses),> 20,4.6,BvBC;BigFootprint;Fed;Frontend;IcMiss;MemoryTLB,,pub/v4.3,0,;bot;EDP;perf,,InTree,,
Bottleneck,Instruction_Fetch_BW,,,,,,,,,,,,,,,,,,,,,,100 * ( Frontend_Bound - ( 1 - #Umisp ) * Fetch_Latency * Mispredicts_Resteers / ##Fetch_Latency - #Assist_Frontend ) - Big_Code,,,,,,,,,,Scaled_Slots,Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end),> 20,5.1,BvFB;Fed;FetchBW;Frontend,,pub/v4.3,0,;bot;EDP;perf,,Tree+#Repeat_Fraction,,
Bottleneck,Data_Cache_Memory_Bandwidth,,,,,,,,100 * ( ( Memory_Bound * ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Bandwidth / ##L3_Miss_Bound ) ) + ( Memory_Bound * ( L3_Bound / ##Memory_Bound ) * ( SQ_Full / ##L3_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( FB_Full / ##L1_Bound ) ) ),,,( 100 * ( ( Memory_Bound * ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Bandwidth / ##L3_Miss_Bound ) ) + ( Memory_Bound * HBM_Bound / ##Memory_Bound ) * MEM_Bandwidth / ##L3_Miss_Bound + ( Memory_Bound * ( L3_Bound / ##Memory_Bound ) * ( SQ_Full / ##L3_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( FB_Full / ##L1_Bound ) ) ) ),,,,,,,,,,,100 * ( ( Memory_Bound * ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Bandwidth / ##L3_Miss_Bound ) ) + ( Memory_Bound * ( L3_Bound / ##Memory_Bound ) * ( SQ_Full / ##L3_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( FB_Full / ##L1_Bound ) ) ),,,,,,,,,,Scaled_Slots,Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks,> 20; $issueBW,4.9,BvMB;Mem;MemoryBW;Offcore,,pub/5.0,0,;bot;EDP;perf,,InTree,,
Bottleneck,Data_Cache_Memory_Latency,,,,,,100 * Memory_Bound * ( ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Latency / ##L3_Miss_Bound ) + ( L3_Bound / ##Memory_Bound ) * ( L3_Hit_Latency / ##L3_Bound ) + ( L2_Bound / ##Memory_Bound ) + ( L1_Bound / ##Memory_Bound ) * ( L1_Latency_Capacity / ##L1_Bound ) ),100 * ( ( Memory_Bound * ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Latency / ##L3_Miss_Bound ) ) + ( Memory_Bound * ( L3_Bound / ##Memory_Bound ) * ( L3_Hit_Latency / ##L3_Bound ) ) + ( Memory_Bound * L2_Bound / ##Memory_Bound ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( L1_Latency_Capacity / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Lock_Latency / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Split_Loads / ##L1_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Split_Stores / ##Store_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Store_Latency / ##Store_Bound ) ) ),100 * ( ( Memory_Bound * ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Latency / ##L3_Miss_Bound ) ) + ( Memory_Bound * ( L3_Bound / ##Memory_Bound ) * ( L3_Hit_Latency / ##L3_Bound ) ) + ( Memory_Bound * L2_Bound / ##Memory_Bound ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( L1_Latency_Dependency / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Lock_Latency / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Split_Loads / ##L1_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Split_Stores / ##Store_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Store_Latency / ##Store_Bound ) ) ),,,100 * ( ( Memory_Bound * ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Latency / ##L3_Miss_Bound ) ) + ( Memory_Bound * HBM_Bound / ##Memory_Bound ) * MEM_Latency / ##L3_Miss_Bound + ( Memory_Bound * ( L3_Bound / ##Memory_Bound ) * ( L3_Hit_Latency / ##L3_Bound ) ) + ( Memory_Bound * L2_Bound / ##Memory_Bound ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( L1_Latency_Dependency / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Lock_Latency / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Split_Loads / ##L1_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Split_Stores / ##Store_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Store_Latency / ##Store_Bound ) ) ),,,,,,,,,,,100 * ( ( Memory_Bound * ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Latency / ##L3_Miss_Bound ) ) + ( Memory_Bound * ( L3_Bound / ##Memory_Bound ) * ( L3_Hit_Latency / ##L3_Bound ) ) + ( Memory_Bound * L2_Bound / ##Memory_Bound ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( L1_Latency_Dependency / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Lock_Latency / ##L1_Bound ) ) + ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( Split_Loads / ##L1_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Split_Stores / ##Store_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( Store_Latency / ##Store_Bound ) ) ),,,,,,,,,,Scaled_Slots,Total pipeline cost of external Memory- or Cache-Latency related bottlenecks,> 20; $issueLat,5,BvML;Mem;MemoryLat;Offcore,,pub/5.0,0,;bot;EDP;perf,,InTree,,
Bottleneck,Memory_Data_TLBs,,,,,,,,,100 * ( ( Memory_Bound * ( L1_Bound / ##Memory_Bound ) * ( DTLB_Load / ##L1_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( DTLB_Store / ##Store_Bound ) ) ),,,,,,,,,,,,,"100 * ( Memory_Bound * ( L1_Bound / max( Memory_Bound , ##Memory_Bound ) ) * ( DTLB_Load / max( L1_Bound , ##L1_Bound ) ) + ( Memory_Bound * ( Store_Bound / ##Memory_Bound ) * ( DTLB_Store / ##Store_Bound ) ) ) ",,,,,,,,,,Scaled_Slots,Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs),> 20; $issueTLB,5,BvMT;Mem;MemoryTLB;Offcore,,pub/5.0,0,;bot;EDP;perf,,InTree,,
Bottleneck,Memory_Synchronization,,,,,,,,,,,,,,,,,,,,,100 * ( Memory_Bound * ( ( L3_Miss_Bound / ##Memory_Bound ) * ( MEM_Latency / ##L3_Miss_Bound ) * Remote_Cache / ##MEM_Latency + ( L3_Bound / ##Memory_Bound ) * ( Contested_Accesses + Data_Sharing ) / ##L3_Bound + ( Store_Bound / ##Memory_Bound ) * False_Sharing / ( ##Store_Bound - Store_Latency )  ) + Machine_Clears * ( 1 - Other_Nukes / ##Machine_Clears ) ) if #DS else 100 * ( Memory_Bound * ( ( L3_Bound / ##Memory_Bound ) * ( Contested_Accesses + Data_Sharing ) / ##L3_Bound + ( Store_Bound / ##Memory_Bound ) * False_Sharing / ( ##Store_Bound - Store_Latency )  ) + Machine_Clears * ( 1 - Other_Nukes / ##Machine_Clears ) ),100 * ( Memory_Bound * ( ( L3_Bound / ##Memory_Bound ) * ( Contested_Accesses + Data_Sharing ) / ##L3_Bound + ( Store_Bound / ##Memory_Bound ) * False_Sharing / ( ##Store_Bound - Store_Latency )  ) + Machine_Clears * ( 1 - Other_Nukes / ##Machine_Clears ) ),,,,,,,,,,Scaled_Slots,Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors),> 10; $issueSyncxn,5.01,BvMS;LockCont;Mem;Offcore,,pub/5.0,0,;bot;EDP;perf,,,,
Bottleneck,Compute_Bound_Est,,,,,,,,,,,,100 * ( ( Core_Bound * Divider / ##Core_Bound ) + ( Core_Bound * AMX_Busy / ##Core_Bound ) + ( Core_Bound * ( Ports_Utilization / ##Core_Bound ) * ( Ports_Utilized_3m / ##Ports_Utilization ) ) ),,,,,,,,,,100 * ( ( Core_Bound * Divider / ##Core_Bound ) + ( Core_Bound * ( Ports_Utilization / ##Core_Bound ) * ( Ports_Utilized_3m / ##Ports_Utilization ) ) ),,,,,,,,,,Scaled_Slots,Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.,> 20; $issueComp,4.8,BvCB;Cor,,pub/5.0,0,;bot;EDP;perf,,Tree+ILP,,
Bottleneck,Irregular_Overhead,,,,,,,,,,,,,,,,,,,,,,100 * ( #Assist_Frontend + #Umisp * Branch_Mispredicts + ( Machine_Clears * Other_Nukes / ##Machine_Clears ) + #Serialize_Core + #Assist_Retired ),,,,,,,,,,Scaled_Slots,"Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)",> 10; $issueMS,5.1,Bad;BvIO;Cor;Ret,,pub/5.0,0,;bot;EDP;perf,,Tree+#Repeat_Fraction,,
Bottleneck,Other_Bottlenecks,,,,,,,,,,,,,,,,,,,,,,100 - ( Big_Code + Instruction_Fetch_BW + Mispredictions + Data_Cache_Memory_Bandwidth + Data_Cache_Memory_Latency + Memory_Data_TLBs + Memory_Synchronization + Compute_Bound_Est + Irregular_Overhead + Branching_Overhead + Useful_Work ) ,,,,,,,,,,Scaled_Slots,Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.,> 20,5,BvOB;Cor;Offcore,,pub/5.0,0,;bot;EDP;perf,,,,
Bottleneck,Branching_Overhead,,,,,,,,,,,,,,,,,,,,,,100 * #Branching_Retired,,,,,,,,,,Scaled_Slots,Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound),> 5,4.8,BvBO;Ret,,pub/5.0,0,;bot;EDP;perf,,Tree+#Branching_Retired,Consider Loop Unrolling or function inlining optimizations,
Bottleneck,Useful_Work,,,,,,,,,,,,,,,,,,,,,,100 * ( Retiring - #Branching_Retired - #Assist_Retired ),,,,,,,,,,Scaled_Slots,"Total pipeline cost of ""useful operations"" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.",> 20,4.8,BvUW;Ret,,pub/5.0,0,;bot;EDP;perf,,InTree,,
.,tree,,,,,,,***,,,,,,,,,,,,,,,,,,,,,,,,,-,-,,5,,,pub,-,;bot;,,,,
FE,Frontend_Bound,,,,,,,PERF_METRICS.FRONTEND_BOUND / #PERF_METRICS_SUM if #PERF_METRICS_MSR else IDQ_BUBBLES.CORE / SLOTS,,,,,,PERF_METRICS.FRONTEND_BOUND / #PERF_METRICS_SUM - INT_MISC.UOP_DROPPING / SLOTS if #PERF_METRICS_MSR else ( IDQ_BUBBLES.CORE - INT_MISC.UOP_DROPPING ) / SLOTS,,,,PERF_METRICS.FRONTEND_BOUND / #PERF_METRICS_SUM - INT_MISC.UOP_DROPPING / SLOTS if #PERF_METRICS_MSR else ( IDQ_UOPS_NOT_DELIVERED.CORE - INT_MISC.UOP_DROPPING ) / SLOTS,,,,,,,,,,,,,IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/LNL ? #NA : FRONTEND_RETIRED.LATENCY_GE_4_PS,Slots,This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.,> 0.15,4.3,BvFB;BvIO;TmaL1;PGO,,pub/v3,L1,;bot;,,,,
FE,,Fetch_Latency,,,,,,PERF_METRICS.FETCH_LATENCY / #PERF_METRICS_SUM if #PERF_METRICS_MSR else IDQ_BUBBLES.FETCH_LATENCY / CLKS,,,,,,( PERF_METRICS.FETCH_LATENCY / #PERF_METRICS_SUM - INT_MISC.UOP_DROPPING / SLOTS ) if #PERF_METRICS_MSR else ( IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE * #Pipeline_Width - INT_MISC.UOP_DROPPING ) / SLOTS,,,,( #Pipeline_Width * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / SLOTS,,,,,#Pipeline_Width * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS,,#Pipeline_Width * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS,,,,,,#Pipeline_Width * #Frontend_Latency_Cycles / SLOTS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? RS_EVENTS.EMPTY_END : FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS,Slots,This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.,> 0.1 & P,4.3,Frontend;TmaL2,,pub/v3,L2,;bot;,,,,
FE,,,ICache_Misses,,,,,ICACHE_DATA.STALLS / CLKS + ISB_Full,,,,,,,,,,ICACHE_DATA.STALLS / CLKS,,,,,( ICACHE_16B.IFDATA_STALL + 2 * ICACHE_16B.IFDATA_STALL:c1:e1 ) / CLKS,,,,ICACHE.IFDATA_STALL / CLKS,,ICACHE.IFETCH_STALL / CLKS - ITLB_Misses,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS,Clocks,This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.,> 0.05 & P,4.6,BigFootprint;BvBC;FetchLat;IcMiss,,pub/v3,L3,;bot;,,,Using compiler's Profile-Guided Optimization (PGO) can reduce i-cache misses through improved hot code layout.,
FE,,,,Code_L2_Hit,,,,,,"max( 0 , FRONTEND_RETIRED.L1I_MISS*$PEBS / CLKS - Code_L2_Miss )",,,,,,,,"max( 0 , ICache_Misses - Code_L2_Miss )",,,,,,,,,,,,,,,Clocks_Retired,This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache.,> 0.05 & P,5,IcMiss;FetchLat;Offcore,,,L4,,,,,
FE,,,,Code_L2_Miss,,,,,,FRONTEND_RETIRED.L2_MISS*$PEBS / CLKS,,,,,,,,OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD / CLKS,,,,,,,,,,,,,,,Clocks_Retired,This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache.,> 0.05 & P,5,IcMiss;FetchLat;Offcore,,,L4,,,,,
FE,,,,ISB_Full,,,,( ICACHE_TAG.STALLS_ISB + ICACHE_TAG.STALLS_INUSE ) / CLKS,,,,,,,,,,,,,,,,,,,,,,,#NA,,Clocks,This metric represents fraction of cycles Icache tag lookup was stalled due to Instruction Stream Buffer (ISB) being full,> 0.05 & P,6,,,,,,,,,
FE,,,ITLB_Misses,,,,,ICACHE_TAG.STALLS / CLKS - ISB_Full,,,,,,,,,,,,,,,ICACHE_TAG.STALLS / CLKS,,,,,,,,#ITLB_Miss_Cycles / CLKS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? ITLB_MISSES.WALK_COMPLETED : FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS,Clocks,This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.,> 0.05 & P,6,BigFootprint;BvBC;FetchLat;MemoryTLB,,pub/v3,L3,;bot;,,,"Consider large 2M pages for code (selectively prefer hot large-size function, due to limited 2M entries). Linux options: standard binaries use libhugetlbfs; Hfsort.",https://github.com/libhugetlbfs/libhugetlbfs;https://research.fb.com/publications/optimizing-function-placement-for-large-scale-data-center-applications-2/
FE,,,,Code_STLB_Hit,,,,,,"max( 0 , FRONTEND_RETIRED.ITLB_MISS*$PEBS / CLKS - Code_STLB_Miss )",,,,,,,,,,,,,"max( 0 , ITLB_Misses - Code_STLB_Miss )",,,,,,,,#NA,,Clocks_Retired,"This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)",> 0.05 & P,5,FetchLat;MemoryTLB,,,L4,,,,,
FE,,,,Code_STLB_Miss,,,,,,FRONTEND_RETIRED.STLB_MISS*$PEBS / CLKS,,,,,,,,,,,,,ITLB_MISSES.WALK_ACTIVE / CLKS,,,,,,,,#NA,,Clocks_Retired,"This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk",> 0.05 & P,5,FetchLat;MemoryTLB,1,,L4,,,,,
FE,,,,,Code_STLB_Miss_4K,,,,,ITLB_MISSES.WALK_ACTIVE / CLKS * ITLB_MISSES.WALK_COMPLETED_4K / ( ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M ),,,,,,,,,,,,,Code_STLB_Miss * ITLB_MISSES.WALK_COMPLETED_4K / ( ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses.,> 0.05 & P,5,FetchLat;MemoryTLB,,,L5,,,ZeroOk,,
FE,,,,,Code_STLB_Miss_2M,,,,,ITLB_MISSES.WALK_ACTIVE / CLKS * ITLB_MISSES.WALK_COMPLETED_2M_4M / ( ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M ),,,,,,,,,,,,,Code_STLB_Miss * ITLB_MISSES.WALK_COMPLETED_2M_4M / ( ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses.,> 0.05 & P,5,FetchLat;MemoryTLB,,,L5,,,ZeroOk,,
FE,,,Branch_Resteers,,,,,,,,,,,INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + Unknown_Branches,,,,,,,,,INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + #BAClear_Cost * BACLEARS.ANY / CLKS,,,,,,,,#BAClear_Cost * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CLKS,BR_MISP_RETIRED.ALL_BRANCHES,Clocks,This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.,> 0.05 & P; ~overlap,4.6,FetchLat,,pub/v3,L3,;bot;,,,,
FE,,,,Mispredicts_Resteers,,,,,,,,,,,,,,,,,,,#Mispred_Clears_Fraction * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS,,BR_MISP_RETIRED.ALL_BRANCHES * Branch_Resteers / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ),,,,,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : INT_MISC.CLEAR_RESTEER_CYCLES,Clocks,This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ,> 0.05 & P; $issueBM,4.3,BadSpec;BrMispredicts;BvMP,,pub/v4.3,L4,;bot;,,,,
FE,,,,Clears_Resteers,,,,,,,,,,,,,,,,,,,( 1 - #Mispred_Clears_Fraction ) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS,,MACHINE_CLEARS.COUNT * Branch_Resteers / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ),,,,,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : INT_MISC.CLEAR_RESTEER_CYCLES,Clocks,This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ,> 0.05 & P; $issueMC,4.3,BadSpec;MachineClears,,pub/v4.3,L4,;bot;,,,,
FE,,,,Unknown_Branches,,,,,,,,,,INT_MISC.UNKNOWN_BRANCH_CYCLES / CLKS,,,,,,,,,#BAClear_Cost * BACLEARS.ANY / CLKS,,Branch_Resteers - Mispredicts_Resteers - Clears_Resteers,,,,,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX/ICL/ICX/TGL/RKL ? BACLEARS.ANY : FRONTEND_RETIRED.UNKNOWN_BRANCH,Clocks,This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches,> 0.05 & P,4.3,BigFootprint;BvBC;FetchLat,,pub/v4.3,L3,;bot;,,,,
FE,,,MS_Switches,,,,,#MS_Switches_Cost * IDQ.MS_SWITCHES / CLKS,,,,,,#MS_Switches_Cost * UOPS_RETIRED.MS:c1:e1 / #Retire_Fraction / CLKS,,,,,,,,,,,,,,,,,#MS_Switches_Cost * IDQ.MS_SWITCHES / CLKS,MTL/ADL/SPR/SPR-HBM ? FRONTEND_RETIRED.MS_FLOWS : IDQ.MS_SWITCHES,Clocks_Estimated,This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.,> 0.05 & P; $issueMC; $issueMS; $issueMV; $issueSO,4.6,FetchLat;MicroSeq,1,pub/v3.4,L3,;bot;,,,,
FE,,,LCP,,,,,,,,,,,,,,,,,,,,DECODE.LCP / CLKS,,,,,,,,ILD_STALL.LCP / CLKS,,Clocks,This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.,> 0.05 & P; $issueFB,4.6,FetchLat,,pub/v4.4,L3,;bot;,,,See section 'Length-Changing Prefixes (LCP)' in Optimization Manual:,http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
FE,,,DSB_Switches,,,,,,,,,,,,,,,,,,,,,,,,,,,,DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : FRONTEND_RETIRED.DSB_MISS_PS,Clocks,This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.,> 0.05 & P; $issueFB,4.3,DSBmiss;FetchLat,,pub/v3.6,L3,;bot;,,,See section 'Optimization for Decoded Icache' in Optimization Manual:,http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
FE,,Fetch_Bandwidth,,,,,,,,,,,,,,,,"max( 0 , Frontend_Bound - Fetch_Latency )",,,,,,,,,,,,,Frontend_Bound - Fetch_Latency,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/LNL/PTL ? #NA : FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2,Slots,This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.,> 0.2; $issueFB,4.7,FetchBW;Frontend;TmaL2,,pub/v3,L2,;bot;,,,,
FE,,,MITE,,,,,"( IDQ.MITE_UOPS:c8:i1:eq1 * max(0,#Pipeline_Width - Fetch_MITE) / #Pipeline_Width + IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS ) * ( IDQ_BUBBLES.STARVATION_CYCLES - IDQ_BUBBLES.FETCH_LATENCY ) ) / CLKS ",,,,,,( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / CORE_CLKS / 2,,,,( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / CORE_CLKS / 2,,,,,,,,,,,( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CORE_CLKS / 2,,,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : FRONTEND_RETIRED.ANY_DSB_MISS,Slots_Estimated,This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.,> 0.1 & P,5.1,DSBmiss;FetchBW,,pub/v4,L3,,,,Consider tuning codegen of 'small hotspots' that can fit in DSB. Read about 'Decoded ICache' in Optimization Manual:,http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
FE,,,,Decoder0_Alone,,,INST_DECODED.DECODERS:c1:eq1 / CLKS,#NA,,,,,,,,,,,,,,,( INST_DECODED.DECODERS:c1 - INST_DECODED.DECODERS:c2 ) / CORE_CLKS / 2,,,,,,,,,,Slots_Estimated,This metric represents fraction of cycles where decoder-0 was the only active decoder,> 0.1 & P; $issueD0,4.5,DSBmiss;FetchBW,,,L4,,,,,
FE,,,,MITE_4wide,,,,,,,,,,#NA,,,,( IDQ.MITE_UOPS:c4 - IDQ.MITE_UOPS:c5 ) / CLKS,,,,,,,,,,,,,,,Core_Clocks,This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline,> 0.05 & P,4.4,DSBmiss;FetchBW,,,L4,,,,,
FE,,,DSB,,,,,"( IDQ.DSB_UOPS:c8:i1:eq1 * max(0,#Pipeline_Width - Fetch_DSB) / #Pipeline_Width + IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS ) * ( IDQ_BUBBLES.STARVATION_CYCLES - IDQ_BUBBLES.FETCH_LATENCY ) ) / CLKS ",,,,,,,,,,,,,,,( IDQ.DSB_CYCLES_ANY  - IDQ.DSB_CYCLES_OK ) / CORE_CLKS / 2,,,,,,( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / CORE_CLKS / 2,,,,Slots_Estimated,This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.,> 0.15 & P,5.1,DSB;FetchBW,,pub/v4,L3,,,,,
FE,,,LSD,,,,#NA,"LSD.UOPS:c8:i1:eq1 * max(0,#Pipeline_Width - Fetch_LSD) / #Pipeline_Width / CLKS",#NA,,,,#NA,,,,#NA,,,#NA,( LSD.CYCLES_ACTIVE - LSD.CYCLES_OK ) / CORE_CLKS / 2,,,,,,,,,,#NA,,Slots_Estimated,This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.,> 0.15 & P,5.1,FetchBW;LSD,,pub/v4,L3,,,,,
FE,,,MS,,,,,IDQ.MS_CYCLES_ANY * ( #Pipeline_Width - IDQ.MS_UOPS / IDQ.MS_CYCLES_ANY ) / SLOTS,,,,,,"max( IDQ.MS_CYCLES_ANY , UOPS_RETIRED.MS:c1 / #Retire_Fraction ) / CORE_CLKS / 2.4",,,,IDQ.MS_UOPS:c1 / CORE_CLKS / 3.3,,,,,#NA,,,,,,,,,,Slots_Estimated,This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details.,> 0.05 & P,5.1,MicroSeq,,pub/v5.1,L3,;bot;,,,,
BAD,Bad_Speculation,,,,,,,"PERF_METRICS.BAD_SPECULATION / #PERF_METRICS_SUM if #PERF_METRICS_MSR else max( 1 - ( Frontend_Bound + Backend_Bound + Retiring ) , 0 )",,,,,,,,,,"max( 1 - ( Frontend_Bound + Backend_Bound + Retiring ) , 0 )",,,,,,,,,,,,,( UOPS_ISSUED.ANY - #Retired_Slots + #Pipeline_Width * #Recovery_Cycles ) / SLOTS,#NA,Slots,This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.,> 0.15,4.1,TmaL1,,pub/v3,L1,;bot;,,,,
BAD,,Branch_Mispredicts,,,,,,,,,,,,PERF_METRICS.BRANCH_MISPREDICTS / #PERF_METRICS_SUM if #PERF_METRICS_MSR else TOPDOWN.BR_MISPREDICT_SLOTS / SLOTS,,,,,,,,,,,,,,,,,#Mispred_Clears_Fraction * Bad_Speculation,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? BR_MISP_RETIRED.ALL_BRANCHES_PS : ICL/ICX/RKL/TGL ? BR_MISP_RETIRED.ALL_BRANCHES : TOPDOWN.BR_MISPREDICT_SLOTS,Slots,This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.,> 0.1 & P; $issueBM,4.3,BadSpec;BrMispredicts;BvMP;TmaL2,,pub/v3,L2,;bot;,,,Using profile feedback in the compiler may help. Please see the Optimization Manual for general strategies for addressing branch misprediction issues.,http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
BAD,,,Cond_NT_Mispredicts,,,,,,,( BR_MISP_RETIRED.COND_NTAKEN / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts,,,,,,,,#NA,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU was stalled due to retired misprediction by non-taken conditional branches.,> 0.05 & P,5,BrMispredicts,,,L3,,,,,
BAD,,,Cond_TK_Mispredicts,,,,,#NA,,( BR_MISP_RETIRED.COND_TAKEN / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts,,,,,,,,#NA,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU was stalled due to misprediction by taken conditional branches.,> 0.05 & P,5,BrMispredicts,,,L3,,,,,
BAD,,,Cond_TK_Bwd_Mispredicts,,,,,( BR_MISP_RETIRED.COND_TAKEN_BWD / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts,,,,,,,,,,,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU was stalled due to misprediction by backward-taken conditional branches.,> 0.05 & P,5,BrMispredicts,,,L3,,,,,
BAD,,,Cond_TK_Fwd_Mispredicts,,,,,( BR_MISP_RETIRED.COND_TAKEN_FWD / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts,,,,,,,,,,,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU was stalled due to misprediction by forward-taken conditional branches.,> 0.05 & P,5,BrMispredicts,,,L3,,,,,
BAD,,,Ind_Call_Mispredicts,,,,,,,( BR_MISP_RETIRED.INDIRECT_CALL / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts,,,,,,,,#NA,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect CALL instructions.,> 0.05 & P,5,BrMispredicts,,,L3,,,,,
BAD,,,Ind_Jump_Mispredicts,,,,( BR_MISP_RETIRED.INDIRECT_JMP / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts,,,"max( ( ( BR_MISP_RETIRED.INDIRECT - BR_MISP_RETIRED.INDIRECT_CALL ) / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts  , 0 )",,,,,,,,#NA,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect JMP instructions.,> 0.05 & P,5,BrMispredicts,,,L3,,,,,
BAD,,,Ret_Mispredicts,,,,,,,( BR_MISP_RETIRED.RET / BR_MISP_RETIRED.ALL_BRANCHES ) * Branch_Mispredicts,,,,,,,,#NA,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU was stalled due to retired misprediction by (indirect) RET instructions.,> 0.05 & P,5,BrMispredicts,,,L3,,,,,
BAD,,,Other_Mispredicts,,,,,,,,,,,,,,,,,,,,"max( Branch_Mispredicts * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 )",,,,,,,,,,Slots,This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).,> 0.05 & P,4.6,BvIO;BrMispredicts,,pub/v4.6,L3,;bot;,,,,
BAD,,Machine_Clears,,,,,,,,,,,,,,,,"max( 0 , Bad_Speculation - Branch_Mispredicts )",,,,,,,,,,,,,Bad_Speculation - Branch_Mispredicts,MACHINE_CLEARS.COUNT,Slots,This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.,> 0.1 & P; $issueMC; $issueSyncxn,4.5,BadSpec;BvMS;MachineClears;TmaL2,,pub/v3,L2,;bot;,,,"See ""Memory Disambiguation"" in Optimization Manual and:",https://software.intel.com/sites/default/files/m/d/4/1/d/8/sma.pdf
BAD,,,Other_Nukes,,,,,,,,,,,,,,,,,,,,"max( Machine_Clears * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 )",,,,,,,,#NA,,Slots,This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.,> 0.05 & P,4.7,BvIO;Machine_Clears,,pub/5.0,L3,;bot;,,,,
BE,Backend_Bound,,,,,,,PERF_METRICS.BACKEND_BOUND / #PERF_METRICS_SUM if #PERF_METRICS_MSR else TOPDOWN.BACKEND_BOUND_SLOTS / SLOTS,,,,,,PERF_METRICS.BACKEND_BOUND / #PERF_METRICS_SUM if #PERF_METRICS_MSR else TOPDOWN.BACKEND_BOUND_SLOTS / SLOTS,,,,PERF_METRICS.BACKEND_BOUND / #PERF_METRICS_SUM + ( #Pipeline_Width * INT_MISC.CLEARS_COUNT ) / SLOTS if #PERF_METRICS_MSR else ( TOPDOWN.BACKEND_BOUND_SLOTS + #Pipeline_Width * INT_MISC.CLEARS_COUNT ) / SLOTS,,,,,1 - Frontend_Bound - ( UOPS_ISSUED.ANY + #Pipeline_Width * #Recovery_Cycles ) / SLOTS,,,,,,,,1 - ( Frontend_Bound + Bad_Speculation + Retiring ),SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? #NA : TOPDOWN.BACKEND_BOUND_SLOTS,Slots,This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.,> 0.2,4.3,BvOB;TmaL1,,pub/v3,L1,;bot;,,,,
BE/Mem,,Memory_Bound,,,,,,,,,,,,PERF_METRICS.MEMORY_BOUND / #PERF_METRICS_SUM if #PERF_METRICS_MSR else TOPDOWN.MEMORY_BOUND_SLOTS / SLOTS,,,,,,,,,,,,,,,,,#Memory_Bound_Fraction * Backend_Bound,#NA,Slots,This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).,> 0.2 & P,4.1,Backend;TmaL2,,pub/v3,L2,;bot;,,,,
BE/Mem,,,L1_Bound,,,,,MEMORY_STALLS.L1 / CLKS,,,,,,"max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / CLKS , 0 )",,,,,,,,,,,"max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CLKS , 0 )",,,,"max( ( #STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_PENDING ) / CLKS , 0 )",,#NA,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L1_HIT_PS : MEM_LOAD_RETIRED.L1_HIT,Stalls,This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache.  The L1D cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.,> 0.1 & P; $issueL1; $issueMC,4.4,CacheHits;MemoryBound;TmaL3mem,,pub/v3,L3,;bot;,,,,
BE/Mem,,,,DTLB_Load,,,,,,"MEM_INST_RETIRED.STLB_HIT_LOADS*min($PEBS, #Mem_STLB_Hit_Cost) / CLKS + Load_STLB_Miss",,,,"min( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT:c1 + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CLKS",,,,,,,,,"min( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT:c1 + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CLKS",,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION:c1 + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED ) / CLKS,,,,,,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION ) / CLKS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS : MEM_INST_RETIRED.STLB_MISS_LOADS_PS,Clocks_Estimated,This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.,> 0.1 & P; $issueTLB,4.4,BvMT;MemoryTLB,1,pub/v3.4,L4,;bot;,,,,#Link: Linux THP pages; similar Windows link.
BE/Mem,,,,,Load_STLB_Hit,,,,,"max( 0 , DTLB_Load - Load_STLB_Miss )",,,,,,,,,,,,,DTLB_Load - Load_STLB_Miss,,,,,,,,#NA,,Clocks_Estimated,"This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",> 0.05 & P,4.2,MemoryTLB,1,pub/5.0,L5,;bot;,,,,
BE/Mem,,,,,Load_STLB_Miss,,,,,,,,,,,,,,,,,,DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS,,,,,,,,#NA,,Clocks_Calculated,"This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",> 0.05 & P,3.6,MemoryTLB,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,,,Load_STLB_Miss_4K,,,,,,,,,,,,,,,,,Load_STLB_Miss * DTLB_LOAD_MISSES.WALK_COMPLETED_4K / ( DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses.,> 0.05 & P,5,MemoryTLB,,,L6,,,ZeroOk,,
BE/Mem,,,,,,Load_STLB_Miss_2M,,,,,,,,,,,,,,,,,Load_STLB_Miss * DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / ( DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses.,> 0.05 & P,5,MemoryTLB,,,L6,,,ZeroOk,,
BE/Mem,,,,,,Load_STLB_Miss_1G,,,,,,,,,,,,,,,,,Load_STLB_Miss * DTLB_LOAD_MISSES.WALK_COMPLETED_1G / ( DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses.,> 0.05 & P,5,MemoryTLB,,,L6,,,ZeroOk,,
BE/Mem,,,,Store_Fwd_Blk,,,,,,,,,,,,,,,,,,,,,,,,,13 * LD_BLOCKS.STORE_FORWARD / CLKS,,,,Clocks_Estimated,This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.,> 0.1 & P,3.3,,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,Store_Early_Blk,,,,LD_BLOCKS.STORE_EARLY:c1 / CLKS,,,,,,#NA,,,,#NA,,,,,,,,,,,#NA,,,,Clocks_Estimated,This metric roughly estimates clocks wasted due to loads blocked due to unknown store address (did not do memory disambiguation) or due to unknown store data,> 0.2,5.1,,1,,4,;bot;,,,GPZv4,
BE/Mem,,,,L1_Latency_Dependency,,,,#NA,,,,,,"min( 2 * ( MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS ) * Dependent_Loads_Weight / 100 , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CLKS",,,,,,,,,"min( 2 * ( MEM_INST_RETIRED.ALL_LOADS_PS - MEM_LOAD_RETIRED.FB_HIT_PS - MEM_LOAD_RETIRED.L1_MISS_PS ) * Dependent_Loads_Weight / 100 , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CLKS",,,,,,,,#NA,LNL ? DEPENDENT_LOADS.ANY : SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L1_HIT_PS : MEM_LOAD_RETIRED.L1_HIT,Clocks_Estimated,This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example.,> 0.1 & P,5,BvML;MemoryLat,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,L1_Latency_Capacity,,,,"MEM_LOAD_RETIRED.L1_HIT_L1*min($PEBS, 9) / CLKS",,,,,,,,,,,,,,,,,,,,,,,#NA,,Clocks_Retired,This metric estimates fraction of cycles with demand load accesses that hit Level 1 after missing Level 0 within the L1D cache.,> 0.1 & P,5,BvML;MemoryLat,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,Lock_Latency,,,,,,MEM_INST_RETIRED.LOCK_LOADS*$PEBS / CLKS,,,,LOCK_CYCLES.CACHE_LOCK_DURATION / CLKS,,,,"( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + #Mem_Lock_St_Fraction * ( #Mem_L2_Store_Cost * L2_RQSTS.RFO_HIT + #ORO_Demand_RFO_C1 ) ) / CLKS",,,,,"( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + #Mem_Lock_St_Fraction * ( #Mem_L2_Store_Cost * L2_RQSTS.RFO_HIT + #ORO_Demand_RFO_C1 ) ) / CLKS",,,,,,#Mem_Lock_St_Fraction * #ORO_Demand_RFO_C1 / CLKS,,#NA,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.LOCK_LOADS_PS : MEM_INST_RETIRED.LOCK_LOADS,Clocks,This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.,> 0.2 & P; $issueRFO,4.3,LockCont;Offcore,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,Split_Loads,,,,,,"MEM_INST_RETIRED.SPLIT_LOADS*min($PEBS, Load_Miss_Real_Latency) / CLKS",,,,MEM_INST_RETIRED.SPLIT_LOADS * Load_Miss_Real_Latency / CLKS,,,,,,,,,,,,,Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS,,13 * LD_BLOCKS.NO_SR / CLKS,,,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.SPLIT_LOADS_PS : MEM_INST_RETIRED.SPLIT_LOADS_PS,Clocks_Calculated,This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ,> 0.3,5,,1,pub/5.0,L4,;bot;,,,Consider aligning data or hot structure fields. See the Optimization Manual for more details,
BE/Mem,,,,4K_Aliasing,,,,,,,,,,#NA,,,,,,,,,,,,,,,LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS,,,,Clocks_Estimated,This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).,> 0.2 & P,3.4,,,pub/5.0,L4,;bot;,,,Consider reducing independent loads/stores accesses with 4K offsets. See the Optimization Manual for more details,
BE/Mem,,,,FB_Full,,,,L1D_MISS.FB_FULL / CLKS,,,,,,,,,,L1D_PEND_MISS.FB_FULL / CLKS,,,,,,,Load_Miss_Real_Latency * L1D_PEND_MISS.FB_FULL:c1 / CLKS,,Load_Miss_Real_Latency * L1D_PEND_MISS.REQUEST_FB_FULL:c1 / CLKS,,Load_Miss_Real_Latency * L1D_PEND_MISS.FB_FULL:c1 / CLKS,,,,Clocks_Calculated,This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).,> 0.3; $issueBW; $issueSL; $issueSmSt,4,BvMB;MemoryBW,,pub/v3.1,L4,;bot;,,,See $issueBW and $issueSL hints. Avoid software prefetches if indeed memory BW limited.,
BE/Mem,,,L2_Bound,,,,,( MEM_LOAD_RETIRED.L2_HIT / ( MEM_LOAD_RETIRED.L2_HIT + MEM_LOAD_MISC_RETIRED.UC * #UC_Scale_Factor ) ) * MEMORY_STALLS.L2 / CLKS,,,,,,( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / CLKS,,,,( #LOAD_L2_HIT / ( #LOAD_L2_HIT + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * #L2_Bound_Ratio,,,,,( #LOAD_L2_HIT / ( #LOAD_L2_HIT + L1D_PEND_MISS.FB_FULL:c1 ) ) * #L2_Bound_Ratio,,( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CLKS,,,,( CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING ) / CLKS,,#NA,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L2_HIT_PS : MEM_LOAD_RETIRED.L2_HIT,Stalls,This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.,> 0.05 & P,4,BvML;CacheHits;MemoryBound;TmaL3mem,,pub/v3,L3,;bot;,,,,
BE/Mem,,,,L2_Hit_Latency,,,,,,"MEM_LOAD_RETIRED.L2_HIT*min($PEBS, #Mem_L2_Hit_Cost) * #FB_Factor / CLKS",,,,,,,,,,,,,#Mem_L2_Hit_Cost * MEM_LOAD_RETIRED.L2_HIT_PS * #FB_Factor / CLKS,,,,,,,,,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L2_HIT_PS : MEM_LOAD_RETIRED.L2_HIT,Clocks_Retired,This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency.,> 0.05 & P,5,MemoryLat,,,L4,,,,,
BE/Mem,,,L3_Bound,,,,,MEMORY_STALLS.L3 / CLKS,,,,,,( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / CLKS,,,,,,,,,( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CLKS,,#Mem_L3_Hit_Fraction * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS,,,,,,#Mem_L3_Hit_Fraction * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS,SNB/JKT/IVB/IVT ? MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS : HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L3_HIT_PS : SKL/SKX/CFL/CLX/CPX/ICL/ICX/RKL/TGL/ADL/SPR/SPR-HBM/EMR/MTL/GNR/LNL/PTL ? MEM_LOAD_RETIRED.L3_HIT_PS : MEM_LOAD_L2_MISS_RETIRED.L3_HIT_SAME_CBB,Stalls,This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.,> 0.05 & P,3.3,CacheHits;MemoryBound;TmaL3mem,,pub/v3,L3,;bot;,,,,
BE/Mem,,,,Contested_Accesses,,,,"( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS*min($PEBS, #Mem_XSNP_Hit_Cost - #Mem_L2_Hit_Cost) + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM*min($PEBS, #Mem_XSNP_HitM_Cost - #Mem_L2_Hit_Cost) ) * #FB_Factor / CLKS",,"( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS*min($PEBS, #Mem_XSNP_Hit_Cost - #Mem_L2_Hit_Cost) + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD*min($PEBS, #Mem_XSNP_HitM_Cost - #Mem_L2_Hit_Cost) * #True_XSNP_HitM_Fraction ) * #FB_Factor / CLKS",,,,,,,,,,,,,( ( #Mem_XSNP_HitM_Cost - #Mem_L2_Hit_Cost ) * #LOAD_XSNP_HITM + ( #Mem_XSNP_Hit_Cost - #Mem_L2_Hit_Cost ) * #LOAD_XSNP_MISS ) * #FB_Factor / CLKS,,,,,,( #Mem_XSNP_HitM_Cost * #LOAD_XSNP_HITM + #Mem_XSNP_Hit_Cost * #LOAD_XSNP_MISS ) / CLKS,,,SNB/JKT ? #NA : IVB/IVT ? MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS : HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS : SKL/SKX/CFL/CLX/CPX/ICL/ICX/RKL ? MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS : TGL/ADL/SPR/SPR-HBM/EMR/MTL/GNR/LNL/PTL ? MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS : MEM_LOAD_L2_MISS_RETIRED.L3.SAME_CBB.HIT_ESF.SNP_MISS;MEM_LOAD_L2_MISS_RETIRED.OTHER_MODULE_L2.SAME_CBB.HIT_M.SNP_FWD,Clocks_Estimated,This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.,> 0.05 & P; $issueSyncxn,4.2,BvMS;DataSharing;LockCont;Offcore;Snoop,1,pub/5.0,L4,;bot;,,ZeroOk,,
BE/Mem,,,,Data_Sharing,,,,"( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD*min($PEBS, #Mem_XSNP_Hit_Cost - #Mem_L2_Hit_Cost) + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD*min($PEBS, #Mem_XSNP_HitM_Cost - #Mem_L2_Hit_Cost) ) * #FB_Factor / CLKS",,"( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD*min($PEBS, #Mem_XSNP_Hit_Cost - #Mem_L2_Hit_Cost) + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD*min($PEBS, #Mem_XSNP_Hit_Cost - #Mem_L2_Hit_Cost) * ( 1 - #True_XSNP_HitM_Fraction ) ) * #FB_Factor / CLKS",,,,,,,,,,,,,( #Mem_XSNP_Hit_Cost - #Mem_L2_Hit_Cost ) * #LOAD_XSNP_HIT * #FB_Factor / CLKS,,,,,,#Mem_XSNP_Hit_Cost * #LOAD_XSNP_HIT / CLKS,,,SNB/JKT ? #NA : IVB/IVT ? MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS : HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS : SKL/SKX/CFL/CLX/CPX/ICL/ICX/RKL ? MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS : TGL/ADL/SPR/SPR-HBM/EMR/MTL/GNR/LNL/PTL ? MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD : MEM_LOAD_L2_MISS_RETIRED.L3.SAME_CBB.HIT_ESF.SNP_HIT_NO_FWD,Clocks_Estimated,This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to L3 data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.,> 0.05 & P; $issueSyncxn,4.2,BvMS;Offcore;Snoop,1,pub/5.0,L4,;bot;,,ZeroOk,,
BE/Mem,,,,L3_Hit_Latency,,,,,,"MEM_LOAD_RETIRED.L3_HIT*min($PEBS, #Mem_XSNP_None_Cost - #Mem_L2_Hit_Cost) * #FB_Factor / CLKS",,,,,,,,,,,,,( #Mem_XSNP_None_Cost - #Mem_L2_Hit_Cost ) * #LOAD_L3_HIT / CLKS,,,,,,#Mem_XSNP_None_Cost * #LOAD_L3_HIT / CLKS,,,SNB/JKT ? #NA : IVB/IVT ? MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS : HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L3_HIT_PS : SKL/SKX/CFL/CLX/CPX/ICL/ICX/RKL/TGL/ADL/SPR/SPR-HBM/EMR/MTL/GNR/LNL/PTL ? MEM_LOAD_RETIRED.L3_HIT_PS : MEM_LOAD_L2_MISS_RETIRED.L3_HIT_SAME_CBB,Clocks_Estimated,This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings.,> 0.1 & P; $issueLat; ~overlap,4.2,BvML;MemoryLat,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,SQ_Full,,,,( XQ.FULL + L1D_MISS.L2_STALLS ) / CLKS,,,,,,( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / CLKS,,,,L1D_PEND_MISS.L2_STALL / CLKS,,,,,,,,,,,#SQ_Full_Cycles / CORE_CLKS,,,,Clocks,This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).,> 0.3 & P; $issueBW,4.3,BvMB;MemoryBW;Offcore,,pub/5.0,L4,;bot;,,,,
BE/Mem,,,HBM_Bound,,,,,,,,#NA,#MEM_Bound_Ratio * OCR.DEMAND_DATA_RD.PMM / OCR.READS_TO_CORE.L3_MISS,,,,,,,,,,,,,,,,,,,#NA,,Stalls,This metric estimates how often the CPU was stalled due to High Bandwidth Memory (HBM) accesses by loads.,> 0.1 & P,4.7,BvMB;BvML;MemoryBound;Offcore;Server;TmaL3mem,,pub/v4.6,L3,;bot;,,,,
BE/Mem,,,L3_Miss_Bound,,,,,#MEM_Bound_Ratio,( #MEM_Bound_Ratio - CXL_Mem_Bound ) if #PMM_App_Direct else #MEM_Bound_Ratio,,#MEM_Bound_Ratio,#MEM_Bound_Ratio - HBM_Bound,,,,,,,,( #MEM_Bound_Ratio - CXL_Mem_Bound ) if #PMM_App_Direct else #MEM_Bound_Ratio,,,#MEM_Bound_Ratio,,( 1 - #Mem_L3_Hit_Fraction ) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS,,,,,,( 1 - #Mem_L3_Hit_Fraction ) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS,SNB ? MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS : IVB/IVT/JKT ? MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS : HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L3_MISS_PS :  SKL/SKX/CFL/CLX/CPX/ICL/ICX/RKL/TGL/ADL/SPR/SPR-HBM/EMR/MTL/GNR/LNL/PTL ? MEM_LOAD_RETIRED.L3_MISS : MEM_LOAD_L2_MISS_RETIRED.L3_MISS,Stalls,This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.,> 0.1 & P,4.7,MemoryBound;TmaL3mem;Offcore,1,pub/v3,L3,;bot;,,,,
BE/Mem,,,,MEM_Bandwidth,,,,,,,,,,,,,,,,,,,,,,,,,,,#ORO_DRD_BW_Cycles / CLKS,,Clocks,This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).,> 0.2 & P; $issueBW,4.7,BvMB;MemoryBW;Offcore,,pub/v3,L4,;bot;,,,"Improve data accesses to reduce cacheline transfers from/to memory. Examples: 1) Consume all bytes of a each cacheline before it is evicted (e.g. reorder structure elements and split non-hot ones), 2) merge computed-limited with BW-limited loops, 3) NUMA optimizations in multi-socket system. Note: software prefetches will not help BW-limited application.",#Link: what is NUMA article
BE/Mem,,,,,MBA_Stalls,,,,,,,,INT_MISC.MBA_STALLS / CLKS,,,,,,,,,,,,,,,,,,,,Clocks,This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).,> 0.1 & P,4.6,MemoryBW;Offcore;Server,,,L5,,,ZeroOk,,
BE/Mem,,,,MEM_Latency,,,,,,,,,,,,,,,,,,,,,,,,,,,#ORO_DRD_Any_Cycles / CLKS - MEM_Bandwidth,,Clocks,This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).,> 0.1 & P; $issueLat,4.7,BvML;MemoryLat;Offcore,,pub/v3,L4,;bot;,,,"Improve data accesses or interleave them with compute. Examples: 1) Data layout re-structuring, 2) Software Prefetches (also through the compiler).",#Link: Data re-layout; SW prefetching; AoS vs. SoA articles.
BE/Mem,,,,,Local_MEM,,,,MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM*$PEBS * #FB_Factor / CLKS,,,,,,,,( #Mem_Local_DRAM_Cost - #Mem_XSNP_None_Cost ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * #FB_Factor / CLKS,,,,,( #Mem_Local_DRAM_Cost - #Mem_XSNP_None_Cost ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * #FB_Factor / CLKS,,,,,,#Mem_Local_DRAM_Cost * #LOAD_LCL_MEM / CLKS,,,#NA,SNB/JKT/IVB/HSW/BDW/SKL/KBL/KBLR/CFL/ICL/TGL/RKL/ADL/MTL/LNL/PTL ? #NA : IVT ? MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS : HSX/BDX ? MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS : MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM,Clocks_Estimated,This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.,> 0.1 & P,4.7,Server,1,pub/5.0,L5,;bot;,,,,
BE/Mem,,,,,Remote_MEM,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM*$PEBS * #FB_Factor / CLKS,,,,,,,,,,,,,( #Mem_Remote_DRAM_Cost - #Mem_XSNP_None_Cost ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * #FB_Factor / CLKS if #DS else #NA,,,,,,#Mem_Remote_DRAM_Cost * #LOAD_RMT_MEM / CLKS,,,#NA,SNB/JKT/IVB/HSW/BDW/SKL/KBL/KBLR/CFL/ICL/TGL/RKL/ADL/MTL/LNL/PTL ? #NA : IVT ? MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM_PS : HSX/BDX ? MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS : MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS,Clocks_Estimated,This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article,> 0.1 & P,5.1,Server;Snoop,1,pub/5.0,L5,;bot;,,,,
BE/Mem,,,,,Remote_Cache,,,,( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM*$PEBS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD*$PEBS ) * #FB_Factor / CLKS,,,,,,,,,,,,,( ( #Mem_Remote_HitM_Cost - #Mem_XSNP_None_Cost ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( #Mem_Remote_Fwd_Cost - #Mem_XSNP_None_Cost ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * #FB_Factor / CLKS if #DS else #NA,,,,,,( #Mem_Remote_HitM_Cost * #LOAD_RMT_HITM + #Mem_Remote_Fwd_Cost * #LOAD_RMT_FWD ) / CLKS,,,#NA,SNB/JKT/IVB/HSW/BDW/SKL/KBL/KBLR/CFL/ICL/TGL/RKL/ADL/MTL/LNL/PTL ? #NA : IVT ? MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD_PS : HSX/BDX ? MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS : MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS,Clocks_Estimated,This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article,> 0.05 & P; $issueSyncxn,5.1,Offcore;Server;Snoop,1,pub/5.0,L5,;bot;,,ZeroOk,,
BE/Mem,,,,UC_Bound,,,,( MEM_LOAD_MISC_RETIRED.UC * #UC_Scale_Factor / (MEM_LOAD_RETIRED.L2_HIT + MEM_LOAD_MISC_RETIRED.UC * #UC_Scale_Factor) ) * MEMORY_STALLS.L2 / CLKS,,,,,,,,,,,,,,,,,,,,,,,#NA,,Stalls,This metric roughly estimates fraction of cycles where the core's performance was likely hurt due to un-chacheable memory,> 0.2 & P; $issueBW,5.2,BvMB;MemoryBW;Offcore,,pub/5.0,L4,;bot;,,,,
BE/Mem,,,CXL_Mem_Bound,,,,,,( ( ( 1 - #Mem_DDR_Hit_Fraction ) * #MEM_Bound_Ratio ) if ( #OneMillion * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_CXL_MEM + MEM_LOAD_RETIRED.LOCAL_CXL_MEM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) if #PMM_App_Direct else #NA,,#NA,#NA,,,,,,,,( ( ( 1 - #Mem_DDR_Hit_Fraction ) * #MEM_Bound_Ratio ) if ( #OneMillion * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) if #PMM_App_Direct else #NA,,,,,,,,,,,#NA,,Stalls,"This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external CXL Memory by loads (e.g. 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory, PMM - Persistent Memory Module [from CLX to SPR] or any other CXL Type3 Memory [EMR onwards]). ",> 0.1 & P,4.8,MemoryBound;Server;TmaL3mem,1,pub/v3.5,L3,;bot;,,ZeroOk,Consider moving data-structure from AEP to DDR memory for better latency/bandwidth,#Link: Opt Guide CR section
BE/Mem,,,Store_Bound,,,,,,,,,,,,,,,EXE_ACTIVITY.BOUND_ON_STORES / CLKS,,,,,EXE_ACTIVITY.BOUND_ON_STORES / CLKS,,,,,,,,RESOURCE_STALLS.SB / CLKS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.ALL_STORES_PS : MEM_INST_RETIRED.ALL_STORES_PS,Stalls,This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.,> 0.2 & P,4.2,MemoryBound;TmaL3mem,,pub/v3,L3,;bot;,,,,
BE/Mem,,,,Store_Latency,,,,,,,,,,,,,,,,,,,,,,,,,( #Store_L2_Hit_Cycles + ( 1 - #Mem_Lock_St_Fraction ) * #ORO_Demand_RFO_C1 ) / CLKS,,#NA,,Clocks_Estimated,This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full),> 0.1 & P; $issueRFO; $issueSL; ~overlap,3.3,BvML;LockCont;MemoryLat;Offcore,1,pub/5.0,L4,;bot;,,,Consider to avoid/reduce unnecessary (or easily load-able/computable) memory store.,
BE/Mem,,,,False_Sharing,,,,,,,,,,,,,( #Mem_Remote_HitM_Cost * OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002 + #Mem_XSNP_HitM_Cost * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM ) / CLKS if #DS else #Mem_XSNP_HitM_Cost * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS,#Mem_XSNP_HitM_Cost * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS,,,,( #Mem_Remote_HitM_Cost * #OCR_all_rfo_l3_miss_remote_hitm + #Mem_XSNP_HitM_Cost * #OCR_all_rfo_l3_hit_snoop_hitm ) / CLKS if #DS else #Mem_XSNP_HitM_Cost * #OCR_all_rfo_l3_hit_snoop_hitm / CLKS,#Mem_XSNP_HitM_Cost * #OCR_all_rfo_l3_hit_snoop_hitm / CLKS,( #Mem_Remote_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + #Mem_XSNP_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE ) / CLKS,#Mem_XSNP_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS,( #Mem_Remote_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + #Mem_XSNP_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE ) / CLKS,#Mem_XSNP_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE / CLKS,( #Mem_Remote_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + #Mem_XSNP_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE ) / CLKS,#Mem_XSNP_HitM_Cost * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE / CLKS,,,SNB/JKT ? #NA : IVB ? MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE : IVT ? MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE;OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM : HSW ? MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE : BDW ? MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM : HSX/BDX ? MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE;OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM : SKX ? MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE : CLX/CPX ? MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE : SKL/KBL/KBLR/CFL ? MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM : CLX/CPX/ICL/ICX/RKL/TGL/ADL/SPR/SPR-HBM/EMR/MTL/GNR/LNL/PTL ? OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM : L2_REQUEST.RFO_HIT_XSNP_HIT_FWD,Clocks_Estimated,This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ,> 0.05 & P; $issueSyncxn,5.02,BvMS;DataSharing;LockCont;Offcore;Snoop,1,pub/5.0,L4,;bot;,,ZeroOk,False Sharing can be easily avoided by padding to make Logical Processors access different lines.,
BE/Mem,,,,Split_Stores,,,,"MEM_INST_RETIRED.SPLIT_STORES*min($PEBS, 1) / CLKS",,"MEM_INST_RETIRED.SPLIT_STORES*min($PEBS, 1) / CLKS",,,,,,,,,,,,,MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS,,,,,,2 * MEM_UOPS_RETIRED.SPLIT_STORES_PS / CORE_CLKS,,,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.SPLIT_STORES_PS : MEM_INST_RETIRED.SPLIT_STORES_PS,Core_Utilization,This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity.,> 0.2 & P; $issueSpSt,4.5,,,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,Streaming_Stores,,,,,,,,,,,,,,9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS,,,,,,,,,,,,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? #NA : ICL/ICX/RKL/TGL/ADL/SPR/SPR-HBM/EMR/MTL/GNR/LNL/PTL ? OCR.STREAMING_WR.ANY_RESPONSE : OMR.STREAMING_WR.ANY_RESPONSE,Clocks_Estimated,This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.,> 0.2 & P; $issueSmSt,5.02,MemoryBW;Offcore,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,DTLB_Store,,,,"MEM_INST_RETIRED.STLB_HIT_STORES*min($PEBS, #Mem_STLB_Hit_Cost)  / CLKS + Store_STLB_Miss",,"MEM_INST_RETIRED.STLB_HIT_STORES*min($PEBS, #Mem_STLB_Hit_Cost)  / CLKS + Store_STLB_Miss",,,,,,,,,,,,,( #Mem_STLB_Hit_Cost * DTLB_STORE_MISSES.STLB_HIT:c1 + DTLB_STORE_MISSES.WALK_ACTIVE ) / CORE_CLKS,,( #Mem_STLB_Hit_Cost * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION:c1 + 7 * DTLB_STORE_MISSES.WALK_COMPLETED ) / CLKS,,,,( #Mem_STLB_Hit_Cost * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION ) / CLKS,,#NA,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.STLB_MISS_STORES_PS : MEM_INST_RETIRED.STLB_MISS_STORES_PS,Clocks_Estimated,This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data.,> 0.05 & P; $issueTLB,4.3,BvMT;MemoryTLB,1,pub/5.0,L4,;bot;,,,,
BE/Mem,,,,,Store_STLB_Hit,,,,,"max( 0 , DTLB_Store - Store_STLB_Miss )",,,,,,,,,,,,,DTLB_Store - Store_STLB_Miss,,,,,,,,#NA,,Clocks_Estimated,"This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",> 0.05 & P,3.6,MemoryTLB,1,,L5,,,,,
BE/Mem,,,,,Store_STLB_Miss,,,DTLB_STORE_MISSES.WALK_ACTIVE / CLKS,,,,,,,,,,,,,,,DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS,,,,,,,,#NA,,Clocks_Calculated,"This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",> 0.05 & P,3.6,MemoryTLB,1,pub/5.0,L5,;bot;,,,,
BE/Mem,,,,,,Store_STLB_Miss_4K,,,,,,,,,,,,,,,,,Store_STLB_Miss * DTLB_STORE_MISSES.WALK_COMPLETED_4K / ( DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses.,> 0.05 & P,5,MemoryTLB,,,L6,,,ZeroOk,,
BE/Mem,,,,,,Store_STLB_Miss_2M,,,,,,,,,,,,,,,,,Store_STLB_Miss * DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M / ( DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses.,> 0.05 & P,5,MemoryTLB,,,L6,,,ZeroOk,,
BE/Mem,,,,,,Store_STLB_Miss_1G,,,,,,,,,,,,,,,,,Store_STLB_Miss * DTLB_STORE_MISSES.WALK_COMPLETED_1G / ( DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G ),,,,,,,,,,Clocks_Estimated,This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses.,> 0.05 & P,5,MemoryTLB,,,L6,,,ZeroOk,,
BE/Core,,Core_Bound,,,,,,,,,,,,,,,,"max( 0 , Backend_Bound - Memory_Bound )",,,,,,,,,,,,,Backend_Bound - Memory_Bound,,Slots,This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).,> 0.1 & P,4.2,Backend;TmaL2;Compute,,pub/v3,L2,;bot;,,,Tip: consider Port Saturation analysis as next step.,
BE/Core,,,Divider,,,,,,,,,,,ARITH.DIV_ACTIVE / CLKS,,,,,,,,,ARITH.DIVIDER_ACTIVE / CLKS,,ARITH.FPU_DIV_ACTIVE / CORE_CLKS,,10 * ARITH.DIVIDER_UOPS / CORE_CLKS,,,,ARITH.FPU_DIV_ACTIVE / CORE_CLKS,SNB/JKT/IVB/IVT/BDW/BDX ? ARITH.FPU_DIV_ACTIVE : HSW/HSX ? ARITH.DIVIDER_UOPS : SKL/SKX/KBLR/CLX/CPX/ICL/ICX/RKL/TGL/ADL/SPR/SPR-HBM ? ARITH.DIVIDER_ACTIVE : ARITH.DIV_ACTIVE,Clocks,This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.,> 0.2 & P,5.02,BvCB;,1,pub/v3,L3,;bot;,,,,
BE/Core,,,,FP_Divider,,,,,,,,,,ARITH.FPDIV_ACTIVE / CLKS,,,,ARITH.FP_DIVIDER_ACTIVE / CLKS,,,,,,,,,,,,,#NA,,Clocks,This metric represents fraction of cycles where the Floating-Point Divider unit was active.,> 0.2 & P,5,,,,L4,,,,,
BE/Core,,,,INT_Divider,,,,,,,,,,,,,,Divider - FP_Divider,,,,,,,,,,,,,#NA,,Clocks,This metric represents fraction of cycles where the Integer Divider unit was active.,> 0.2 & P,5,,,,L4,,,,,
BE/Core,,,Serializing_Operation,,,,,( BE_STALLS.SCOREBOARD + CPU_CLK_UNHALTED.C02 ) / CLKS,,,,,,RESOURCE_STALLS.SCOREBOARD / CLKS + C02_Wait,,,,RESOURCE_STALLS.SCOREBOARD / CLKS,,,,,PARTIAL_RAT_STALLS.SCOREBOARD / CLKS,,,,,,,,#NA,LNL/ARL/PTL ? BE_STALLS.SCOREBOARD : SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? PARTIAL_RAT_STALLS.SCOREBOARD : RESOURCE_STALLS.SCOREBOARD,Clocks,This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.,> 0.1 & P; $issueSO,4.7,BvIO;PortsUtil,,pub/v3.4,L3,;bot;,,,,
BE/Core,,,,Slow_Pause,,,,,,,,,,CPU_CLK_UNHALTED.PAUSE / CLKS,,,37 * MISC_RETIRED.PAUSE_INST / CLKS,140 * MISC_RETIRED.PAUSE_INST / CLKS,174 * ROB_MISC_EVENTS.PAUSE_INST / CLKS,40 * ROB_MISC_EVENTS.PAUSE_INST / CLKS,140 * ROB_MISC_EVENTS.PAUSE_INST / CLKS,,,,,,,,,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/SKX ? #NA : KBLR/CFL/CLX/CPX ? ROB_MISC_EVENTS.PAUSE_INST : ICL/ICX/RKL/TGL ? MISC_RETIRED.PAUSE_INST : CPU_CLK_UNHALTED.PAUSE_INST,Clocks,This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.,> 0.05 & P,4.3,,,,L4,;,,,,
BE/Core,,,,C01_Wait,,,,,,,,,,CPU_CLK_UNHALTED.C01 / CLKS,,,,,,,,,,,,,,,,,,,Clocks,This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).,> 0.05 & P,4.9,C0Wait,,,L4,,,ZeroOk,,
BE/Core,,,,C02_Wait,,,,,,,,,,CPU_CLK_UNHALTED.C02 / CLKS,,,,,,,,,,,,,,,,,,,Clocks,This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).,> 0.05 & P,4.9,C0Wait,,pub/5.0,L4,;bot;,,ZeroOk,,
BE/Core,,,,Memory_Fence,,,,,,,,,,13 * MISC2_RETIRED.LFENCE / CLKS,,,,,,,,,,,,,,,,,,,Clocks,This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.,> 0.05 & P,4.3,,1,,L4,,,,,
BE/Core,,,AMX_Busy,,,,,,,,,,EXE.AMX_BUSY / CORE_CLKS,,,,,,,,,,,,,,,,,,,,Core_Clocks,This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations,> 0.5 & P,4.7,BvCB;Compute;HPC;Server,,pub/v4.6,L3,;bot;,,,,
BE/Core,,,Ports_Utilization,,,,,,,,,,,#Core_Bound_Cycles / CLKS if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else #Few_Uops_Executed_Threshold / CLKS,,,,,,,,,#Core_Bound_Cycles / CLKS if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else #Few_Uops_Executed_Threshold / CLKS,,( #Backend_Bound_Cycles - RESOURCE_STALLS.SB -  CYCLE_ACTIVITY.STALLS_MEM_ANY ) / CLKS,,,,,,( #Backend_Bound_Cycles - RESOURCE_STALLS.SB -  #STALLS_MEM_ANY ) / CLKS,,Clocks,This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.,> 0.15 & P,4.7,PortsUtil,,pub/v3,L3,;bot;,,,Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.,
BE/Core,,,,Ports_Utilized_0,,,,EXE_ACTIVITY.EXE_BOUND_0_PORTS / CLKS,,"max( EXE_ACTIVITY.EXE_BOUND_0_PORTS - RESOURCE_STALLS.SCOREBOARD , 0 ) / CLKS",,,,"( EXE_ACTIVITY.EXE_BOUND_0_PORTS + max( RS.EMPTY_RESOURCE - RESOURCE_STALLS.SCOREBOARD , 0 ) ) / CLKS * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / CLKS",EXE_ACTIVITY.EXE_BOUND_0_PORTS / CLKS,,,EXE_ACTIVITY.3_PORTS_UTIL:u0x80 / CLKS,,,,,EXE_ACTIVITY.EXE_BOUND_0_PORTS / CLKS,,,,,,#Cycles_0_Ports_Utilized / CORE_CLKS,,#NA,,Clocks,"This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",> 0.2 & P,5,PortsUtil,,pub/5.0,L4,;bot;,,,Check assembly view and Appendix C in Optimization Manual to find out instructions with say 5 or more cycles latency.,http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
BE/Core,,,,,Mixing_Vectors,,,,,,,,,160 * ASSISTS.SSE_AVX_MIX / CLKS,,,,,,,,,UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY,,,,,,,,#NA,,Clocks,This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.,> 0.05; $issueMV,4.6,,1,,L5,,,,,
BE/Core,,,,Ports_Utilized_1,,,,,,,,,,,,,,EXE_ACTIVITY.1_PORTS_UTIL / CLKS,,,,,,,,,,,#Cycles_1_Port_Utilized / CORE_CLKS,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? #NA : EXE_ACTIVITY.1_PORTS_UTIL,Clocks,"This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",> 0.2 & P; $issueL1,4,PortsUtil,,pub/5.0,L4,;bot;,,,,
BE/Core,,,,Ports_Utilized_2,,,,,,,,,,,,,,EXE_ACTIVITY.2_PORTS_UTIL / CLKS,,,,,,,,,,,#Cycles_2_Ports_Utilized / CORE_CLKS,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? #NA : EXE_ACTIVITY.2_PORTS_UTIL,Clocks,"This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",> 0.15 & P; $issue2P,4.2,PortsUtil,,pub/5.0,L4,;bot;,,,,
BE/Core,,,,Ports_Utilized_3m,,,,,,,,,,,,,,UOPS_EXECUTED.CYCLES_GE_3 / CLKS,,,,,,,,,,,#Cycles_3m_Ports_Utilized / CORE_CLKS,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? #NA : UOPS_EXECUTED.CYCLES_GE_3,Clocks,"This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",> 0.4 & P,4.7,BvCB;PortsUtil,,pub/5.0,L4,;bot;,,,,
BE/Core,,,,,ALU_Op_Utilization,,,UOPS_DISPATCHED.ALU / ( 6 * CLKS ),,,,,,( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6 ) / ( 5 * CORE_CLKS ),,,,( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6 ) / ( 4 * CORE_CLKS ),,,,,,,,,( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * CORE_CLKS ),,( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 ) / ( 3 * CORE_CLKS ),,,,Core_Execution,This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.,> 0.4,4.3,,,,L5,,,,,
BE/Core,,,,,,Port_0,,#NA,,,,,,,,,,UOPS_DISPATCHED.PORT_0 / CORE_CLKS,,,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS,,,IVB/IVT/HSW/HSX/BDW/BDX/SKL/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_0 : ICL/ICX/RKL/TGL/ADL/SPR/MTL/GNR ? UOPS_DISPATCHED.PORT_0 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch),> 0.6; $issue2P,4.2,Compute,,,L6,,,,,
BE/Core,,,,,,Port_1,,#NA,,,,,,,,,,UOPS_DISPATCHED.PORT_1 / CORE_CLKS,,,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS,,,IVB/IVT/HSW/HSX/BDW/BDX/SKL/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_1 : ICL/ICX/RKL/TGL/ADL/SPR/MTL/GNR ? UOPS_DISPATCHED.PORT_1 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU),> 0.6; $issue2P,4.2,,,,L6,,,,,
BE/Core,,,,,,Port_5,,,,,,,,#NA,,,,UOPS_DISPATCHED.PORT_5 / CORE_CLKS,,,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS,,,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_5 : ICL/ICX/TGL/RKL ? UOPS_DISPATCHED.PORT_5 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU),> 0.6; $issue2P,4.2,,,,L6,,,,See section 'Handling Port 5 Pressure' in Optimization Manual:,http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
BE/Core,,,,,,Port_6,,#NA,,,,,,,,,,UOPS_DISPATCHED.PORT_6 / CORE_CLKS,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS,,,,#NA,IVB/IVT/HSW/HSX/BDW/BDX/SKL/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_1 : ICL/ICX/RKL/TGL/ADL/SPR/MTL/GNR ? UOPS_DISPATCHED.PORT_1 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU),> 0.6; $issue2P,4.6,,,,L6,,,,,
BE/Core,,,,,Load_Op_Utilization,,,UOPS_DISPATCHED.LOAD / ( 3 * CLKS ),,,,,,UOPS_DISPATCHED.PORT_2_3_10 / ( 3 * CORE_CLKS ),,,,UOPS_DISPATCHED.PORT_2_3 / ( 2 * CORE_CLKS ),,,,,,,,,( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * CORE_CLKS ),,( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * CORE_CLKS ),,,LNL/PTL ? UOPS_DISPATCHED.LOAD : SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? #NA : ICL/ICX/TGL/RKL ? UOPS_DISPATCHED.PORT_2_3 : UOPS_DISPATCHED.PORT_2_3_10,Core_Execution,This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations,> 0.6,4.3,,,,L5,,,,,
BE/Core,,,,,,Port_2,,,,,,,,,,,,#NA,,,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS,,,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_2 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads),> 0.6,3.4,,,,L6,,,,,
BE/Core,,,,,,Port_3,,,,,,,,,,,,#NA,,,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS,,,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_3 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads),> 0.6,3.4,,,,L6,,,,,
BE/Core,,,,,Store_Op_Utilization,,,( UOPS_DISPATCHED.STD + UOPS_DISPATCHED.STA ) / ( 7 * CLKS ),,,,,,,,,,( UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8 ) / ( 4 * CORE_CLKS ),,,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS,,,LNL/PTL ? UOPS_DISPATCHED.STD;UOPS_DISPATCHED.STA : SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? #NA : UOPS_DISPATCHED.PORT_7_8,Core_Execution,This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations,> 0.6,4.1,,,,L5,,,,,
BE/Core,,,,,,Port_4,,,,,,,,,,,,#NA,,,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS,,,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_4 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data),> 0.6; $issueSpSt,3.4,,,,L6,,,,,
BE/Core,,,,,,Port_7,,,,,,,,,,,,#NA,,,,,,,,,UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS,,,,#NA,SNB/JKT/IVB/IVT ? #NA : HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? UOPS_DISPATCHED_PORT.PORT_7 : #NA,Core_Clocks,This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address),> 0.6,3.4,,,,L6,,,,,
RET,Retiring,,,,,,,,,,,,,,,,,PERF_METRICS.RETIRING / #PERF_METRICS_SUM if #PERF_METRICS_MSR else UOPS_RETIRED.SLOTS / SLOTS,,,,,,,,,,,,,#Retired_Slots / SLOTS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? UOPS_RETIRED.RETIRE_SLOTS : UOPS_RETIRED.SLOTS,Slots,This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ,(> 0.7 | Heavy_Operations),4.3,BvUW;TmaL1,,pub/v3,L1,;bot;,,,A high Retiring value for non-vectorized code may be a good hint for programmer to consider vectorizing his code.  Doing so essentially lets more computations be done without significantly increasing number of instructions thus improving the performance.,
RET,,Light_Operations,,,,,,,,,,,,,,,,"max( 0 , Retiring - Heavy_Operations )",,,,,,,,,,,,,Retiring - Heavy_Operations,INST_RETIRED.PREC_DIST,Slots,This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .),> 0.6,4.6,Retire;TmaL2,,pub/v3,L2,;bot;,,,Focus on techniques that reduce instruction count or result in more efficient instructions generation such as vectorization,  #Link: auto-Vectorization options of Intel/other compilers.
RET,,,FP_Arith,,,,,,,,,,X87_Use + FP_Scalar + FP_Vector,,,,,,,,,,,,X87_Use + FP_Scalar + FP_Vector,,#NA,,,,X87_Use + FP_Scalar + FP_Vector,,Uops,"This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of ""Uops"" CountDomain and FMA double-counting.",> 0.2 & P,4.7,HPC,,pub/v3,L3,;,,,,
RET,,,,X87_Use,,,,,,,,,,,,,,,,,,,Retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD,,INST_RETIRED.X87 * UopPI / #Retired_Slots,,#NA,,#Retired_Slots * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD,,#Retired_Slots * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD,,Uops,This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.,> 0.1 & P,4.6,Compute,,,L3,;,,,Tip: consider compiler flags to generate newer AVX (or SSE) instruction sets; which typically perform better and feature vectors.,
RET,,,,FP_Scalar,,,,,,,,,,,,,,,,,,,,,#FP_Arith_Scalar / #Retired_Slots,,#NA,,#FP_Arith_Scalar / UOPS_EXECUTED.THREAD,,#FP_Arith_Scalar / UOPS_DISPATCHED.THREAD,,Uops,This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.,> 0.1 & P; $issue2P,4.8,Compute;Flops,,pub/v3,L3,;,,,Investigate what limits (compiler) generation of vector code.,
RET,,,,FP_Vector,,,,,,,,,,,,,,,,,,,,,#FP_Arith_Vector / #Retired_Slots,,#NA,,#FP_Arith_Vector / UOPS_EXECUTED.THREAD,,#FP_Arith_Vector / UOPS_DISPATCHED.THREAD,,Uops,This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.,> 0.1 & P; $issue2P,4.8,Compute;Flops,1,pub/v3,L3,;,,,Check if vector width is expected ,
RET,,,,,FP_Vector_128b,,,( FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE ) / #Retired_Slots,,,,,( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF ) / #Retired_Slots if #FP16 else ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / #Retired_Slots,,,,,( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / #Retired_Slots,( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16 ) / #Retired_Slots,,,,,,( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / #Retired_Slots,,#NA,,( FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE ) / UOPS_EXECUTED.THREAD,,( FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE ) / UOPS_DISPATCHED.THREAD,,Uops,This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL.,> 0.1 & P; $issue2P,4.8,Compute;Flops,1,,L5,,,,Try to exploit wider vector length,
RET,,,,,FP_Vector_256b,,,FP_ARITH_OPS_RETIRED.VECTOR_256B / #Retired_Slots,,,,,( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF ) / #Retired_Slots if #FP16 else ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / #Retired_Slots,,,,,( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / #Retired_Slots,( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16 ) / #Retired_Slots,,,,,,( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / #Retired_Slots,,#NA,,( SIMD_FP_256.PACKED_DOUBLE + SIMD_FP_256.PACKED_SINGLE ) / UOPS_EXECUTED.THREAD,,( SIMD_FP_256.PACKED_DOUBLE + SIMD_FP_256.PACKED_SINGLE ) / UOPS_DISPATCHED.THREAD,,Uops,This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL.,> 0.1 & P; $issue2P,4.8,Compute;Flops,1,,L5,,,,Try to exploit wider vector length,
RET,,,,,FP_Vector_512b,,,,,,,,( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF ) / #Retired_Slots if #FP16 else ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / #Retired_Slots,#NA,,,,( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / #Retired_Slots,( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16 ) / #Retired_Slots,,,( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / #Retired_Slots,,,,,,,,,#NA,,Uops,This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.,> 0.1 & P; $issue2P,4.8,Compute;Flops,1,,L5,,,ZeroOk,,
RET,,,Int_Operations,,,,,,,,,,Int_Vector_128b + Int_Vector_256b,Int_Vector_128b + Int_Vector_256b,,,,,,,,,,,,,,,,,,,Uops,"This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of ""Uops"" CountDomain.",> 0.1 & P,4.7,Pipeline,,,L3,,,,,
RET,,,,Int_Vector_128b,,,,INT_VEC_RETIRED.128BIT / #Retired_Slots,,,,,,( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / #Retired_Slots,,,,,,,,,,,,,,,,,,,Uops,This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.,> 0.1 & P; $issue2P,4.4,Compute;IntVector;Pipeline,,,L3,,,,,
RET,,,,Int_Vector_256b,,,,INT_VEC_RETIRED.256BIT / #Retired_Slots,,,,,,( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / #Retired_Slots,,,,,,,,,,,,,,,,,,,Uops,This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.,> 0.1 & P; $issue2P,4.7,Compute;IntVector;Pipeline,,,L3,,,,,
RET,,,Memory_Operations,,,,,,,,,,,Light_Operations * MEM_UOP_RETIRED.ANY / #Retired_Slots,,,,,,,,,Light_Operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY,,,,,,,,,,Slots,This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.,> 0.1 & P,4.4,Pipeline,,pub/v4.4,L3,,,,,
RET,,,Fused_Instructions,,,,,,,,,,,Light_Operations * INST_RETIRED.MACRO_FUSED / #Retired_Slots,,,,#NA,,,,,Light_Operations * UOPS_RETIRED.MACRO_FUSED / #Retired_Slots,,,,,,,,,,Slots,This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)},> 0.1 & P,4.7,Branches;BvBO;Pipeline,,,L3,,,,See section 'Optimizing for Macro-fusion' in Optimization Manual:,
RET,,,Non_Fused_Branches,,,,,Light_Operations * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.BR_FUSED ) / #Retired_Slots,,,,,,Light_Operations * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / #Retired_Slots,,,,#NA,,,,,Light_Operations * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / #Retired_Slots,,,,,,,,,,Slots,This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.,> 0.1 & P,4.7,Branches;BvBO;Pipeline,,,L3,,,,,
RET,,,Branch_Instructions,,,,,,,,,,,#NA,,,,Light_Operations * BR_INST_RETIRED.ALL_BRANCHES / #Retired_Slots,,,,,#NA,,,,,,,,,,Slots,This metric represents fraction of slots where the CPU was retiring branch instructions.,> 0.1 & P,4.7,Branches;BvBO;Pipeline,,,L3,,,,,
RET,,,Other_Light_Ops,,,,,,,,,,,,,,,,,,,,"max( 0 , Light_Operations - #Light_Ops_Sum )",,,,,,,,#NA,,Slots,This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting,> 0.3 & P,4.7,Pipeline,,pub/v3,L3,,,,,
RET,,,,Nop_Instructions,,,,,,,,,,,,,,,,,,,Light_Operations * INST_RETIRED.NOP / #Retired_Slots,,,,,,,,,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : SKL/SKX/KBL/CLX/CPX ? INST_RETIRED.NOP_PS : INST_RETIRED.NOP,Slots,This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.,> 0.1 & P,4.9,BvBO;Pipeline,,pub/v4.3,L4,,,,Improve Codegen by correctly placing NOPs outside hot sections (e.g. outside loop body).,
RET,,,,Shuffles_256b,,,,,,,,,,Light_Operations * INT_VEC_RETIRED.SHUFFLES / #Retired_Slots,,,,,,,,,,,,,,,,,,,Slots,"This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross ""vector lane"" data transfers.",> 0.1 & P,4.7,HPC;Pipeline,,,L4,,,,,
RET,,Heavy_Operations,,,,,,,,,,,,PERF_METRICS.HEAVY_OPERATIONS / #PERF_METRICS_SUM if #PERF_METRICS_MSR else UOPS_RETIRED.HEAVY / SLOTS,,,,Microcode_Sequencer + Retiring * ( UOPS_DECODED.DEC0 - UOPS_DECODED.DEC0:c1 ) / IDQ.MITE_UOPS,,,,,( #Retired_Slots + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / SLOTS,,,,,,,,Microcode_Sequencer,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX/ICL/ICX/RKL/TGL ? #NA : UOPS_RETIRED.HEAVY,Slots,This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+]),> 0.1,4.3,Retire;TmaL2,,pub/v4.1,L2,;bot;,,,,
RET,,,Few_Uops_Instructions,,,,,,,,,,,"max( 0 , Heavy_Operations - Microcode_Sequencer )",,,,,,,,,Heavy_Operations - Microcode_Sequencer,,,,,,,,,,Slots,This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.,> 0.05 & P; $issueD0,5,,,pub/5.0,L3,;bot;,,,,
RET,,,Microcode_Sequencer,,,,,,,,,,,UOPS_RETIRED.MS / SLOTS,,,,,,,,,,,,,,,,,#Retire_Fraction * IDQ.MS_UOPS / SLOTS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX/SKL/KBL/KBLR/CFL/SKX/CLX/CPX/ICL/ICX/TGL/RKL ? IDQ.MS_UOPS : UOPS_RETIRED.MS,Slots,This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.,> 0.05 & P; $issueMC; $issueMS,4.5,MicroSeq,,pub/v3,L3,;bot;,,,, #Link: repeat move strings
RET,,,,Assists,,,,,,,,,,#Avg_Assist_Cost * ASSISTS.ANY / SLOTS,,,,#Avg_Assist_Cost * ASSISTS.ANY / SLOTS,,,,,#Avg_Assist_Cost * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / SLOTS,,,,,,#Avg_Assist_Cost * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS,,#NA,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? OTHER_ASSISTS.ANY_WB_ASSIST : SKL/KBL/KBLR/CFL/SKX/CLX/CPX ? OTHER_ASSISTS.ANY : ASSISTS.ANY,Slots_Estimated,This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.,> 0.1 & P,4.6,BvIO;,1,pub/v4.6,L4,;bot;,,,,
RET,,,,,Page_Faults,,,,,,,,,99 * ASSISTS.PAGE_FAULT / SLOTS,,,,,,,,,,,,,,,,,,,Slots_Estimated,This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.,> 0.05,4.4,,,,L5,,,,,
RET,,,,,FP_Assists,,,,,,,,,30 * ASSISTS.FP / SLOTS,,,,34 * ASSISTS.FP / SLOTS,,,,,34 * FP_ASSIST.ANY / SLOTS,,,,,,,,,,Slots_Estimated,This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).,> 0.1,4.6,HPC,,,L5,,,ZeroOk,"Consider DAZ (Denormals Are Zero) and/or FTZ (Flush To Zero) options in your compiler; ""-ffast-math"" with -O2 in GCC for example. This option may improve performance if the denormal values are not critical in your application. Also note that the DAZ and FTZ modes are not compatible with the IEEE Standard 754.",https://www.intel.com/content/www/us/en/develop/documentation/vtune-help/top/reference/cpu-metrics-reference/bad-speculation-back-end-bound-pipeline-slots/fp-assists.html
RET,,,,,AVX_Assists,,,,,,,,,63 * ASSISTS.SSE_AVX_MIX / SLOTS,,,,,,,,,,,,,,,,,,,Slots_Estimated,This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ,> 0.1,4.6,HPC,,,L5,,,ZeroOk,,
RET,,,,CISC,,,,,,,,,,,,,,,,,,,,,,,,,"max( 0 , Microcode_Sequencer - Assists )",,#NA,MTL/ADL/SPR/SPR-HBM ? FRONTEND_RETIRED.MS_FLOWS : #NA,Slots,This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.,> 0.1 & P,4.4,,,,L4,,,,,
.,metrics,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,-,-,,2.5,,,pub/v3,-,;bot;,,,,
Info.Botlnk.L0,Core_Bound_Likely,,,,,,,#NA,,,,,,,,,,,,,,,100 * ( 1 - Core_Bound / Ports_Utilization if Core_Bound < Ports_Utilization else 1 ) if SMT_2T_Utilization > 0.5 else 0,,,,,,,,,,Metric,Probability of Core Bound bottleneck hidden by SMT-profiling artifacts,> 0.5,4.7,Cor;SMT,1,,0,,,InTree+SMT_2T_Utilization,Tip: consider analysis with SMT disabled,
Info.Thread,IPC,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / CLKS,,Metric,Instructions Per Cycle (per Logical Processor),,4.3,Ret;Summary,#Pipeline_Width + 2,pub/v3,L1,;bot;EDP;perf;VTune,,,,
Info.Thread,UopPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,#Retired_Slots / INST_RETIRED.ANY,,Metric,Uops Per Instruction,> 1.05,4.5,Pipeline;Ret;Retire,2,pub/v3,L1,;EDP;perf,,,,
Info.Thread,UpTB,,,,,,,,,,,,,,,,,,,,,,,,,,,,#Retired_Slots / BR_INST_RETIRED.NEAR_TAKEN,,,,Metric,Uops per taken branch,< #Pipeline_Width * 1.5,4.8,Branches;Fed;FetchBW,,pub/5.0,i,;bot;perf,,,,
Info.Thread,CPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,1 / IPC,,Metric,Cycles Per Instruction (per Logical Processor),,2.7,Pipeline;Mem,,pub/v3,i,;EDP;perf;VTune,,,,
Info.Thread,CLKS,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD,,Count,Per-Logical Processor actual clocks when the Logical Processor is active.,,4.2,Pipeline,,pub/v3,L1,;bot;EDP;perf;VTune,,,,
Info.Thread,SLOTS,,,,,,,TOPDOWN.SLOTS:perf_metrics if #PERF_METRICS_MSR else TOPDOWN.SLOTS_P,,,,,,,,,,TOPDOWN.SLOTS:perf_metrics if #PERF_METRICS_MSR else TOPDOWN.SLOTS,,,,,,,,,,,,,#Pipeline_Width * CORE_CLKS,,Count,Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward),,4.3,TmaL1,,pub/v3,L1,;bot;EDP;perf;VTune,,,,
Info.Thread,Slots_Utilization,,,,,,,#NA,,,,,,,,,,SLOTS / ( TOPDOWN.SLOTS:percore / 2 ) if #SMT_on else 1,,,,,,,,,,,,,#NA,,Metric,Fraction of Physical Core issue-slots utilized by this Logical Processor,,4.1,SMT;TmaL1,1,,i,,,,,
Info.Thread,Execute_per_Issue,,,,,,,,,,,,,,,,,,,,,,,,UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY,,#NA,,UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY,,UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY,,Metric,"The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of ""execute"" at rename stage.",,4.3,Cor;Pipeline,,,,,,,,
Info.Core,CoreIPC,,,,,,,#NA,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / CORE_CLKS,,Core_Metric,Instructions Per Cycle across hyper-threads (per physical core),,4.3,Ret;SMT;TmaL1,#Pipeline_Width + 2,pub/v3,1,;EDP;perf,,,,
Info.Core,FLOPc,,,,,,,#FLOP_Count / CLKS,,,,,,,,,,,,,,,,,#FLOP_Count / CORE_CLKS,,#NA,,,,#FLOP_Count / CORE_CLKS,,Core_Metric,Floating Point Operations Per Cycle,,4.8,Ret;Flops,10,pub/v3,i,;perf,,,,
Info.Core,FP_Arith_Utilization,,,,,,,( FP_ARITH_DISPATCHED.V0 + FP_ARITH_DISPATCHED.V1 + FP_ARITH_DISPATCHED.V2 + FP_ARITH_DISPATCHED.V3 ) / ( 4 * CLKS ),,,,,,( FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5 ) / ( 2 * CORE_CLKS ),,,,,,,,,,,( #FP_Arith_Scalar + #FP_Arith_Vector ) / ( 2 * CORE_CLKS ),,,,,,#NA,,Core_Metric,Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).,,4.8,Cor;Flops;HPC,2,,i,;EDP,,,,
Info.Core,ILP,,,,,,,,,,,,,,,,,,,,,,,,UOPS_EXECUTED.THREAD / UOPS_EXECUTED.THREAD:c1,,( UOPS_EXECUTED.CORE / 2 / #Execute_Cycles ) if #SMT_on else UOPS_EXECUTED.CORE / #Execute_Cycles,,UOPS_EXECUTED.THREAD / UOPS_EXECUTED.THREAD:c1,,UOPS_DISPATCHED.THREAD / #Execute_Cycles,,Metric,Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor),,4.7,Backend;Cor;Pipeline;PortsUtil,#Exe_Ports,pub/v3,i,;EDP;perf,,,,
Info.Core,EPC,,,,,,,,,,,,,,,,,,,,,,UOPS_EXECUTED.THREAD / CLKS,,,,,,,,,,Metric,uops Executed per Cycle,,4.6,Power,20,,,;EDP;perf,,,,
Info.Core,CORE_CLKS,,,,,,,#NA,,,,,,,,,,CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CLKS,,,,,,,,,,,,,( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) if #EBS_Mode else ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CLKS,,Count,Core actual clocks when any Logical Processor is active on the Physical Core,,4.1,SMT,,pub/v3,1,;bot;perf;vtune,,,,
Info.Inst_Mix,IpLoad,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS,,,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS_PS,,,,Inst_Metric,Instructions per Load (lower number means higher occurrence rate),< 3,4.6,InsType,,pub/v3.2,i,;perf,,,Tip: reduce memory accesses,#Link Opt Guide section: Minimize Register Spills
Info.Inst_Mix,IpStore,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES,,,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES_PS,,,,Inst_Metric,Instructions per Store (lower number means higher occurrence rate),< 8,4.6,InsType,,pub/v3.2,i,;perf,,,Tip: reduce memory accesses,#Link Opt Guide section: Minimize Register Spills
Info.Inst_Mix,IpBranch,,,,,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,,Inst_Metric,Instructions per Branch (lower number means higher occurrence rate),< 8,3.2,Branches;Fed;InsType,,pub/v3.2,i,;perf,,,,
Info.Inst_Mix,IpCall,,,,,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL,,,,Inst_Metric,Instructions per (near) call (lower number means higher occurrence rate),< 200,4.7,Branches;Fed;PGO,,pub/v3.4,i,;perf,,,,
Info.Inst_Mix,IpTB,,,,,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN,,,,Inst_Metric,Instructions per taken branch,< #Pipeline_Width * 2 + 1; $issueFB,4.5,Branches;Fed;FetchBW;Frontend;PGO,,pub/v3.2,i,;EDP;perf,,,,
Info.Inst_Mix,BpTkBranch,,,,,,,,,,,,,,,,,,,,,,,,,,,,BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN,,,,Metric,Branch instructions per taken branch. ,,4,Branches;Fed;PGO,,pub/v3.2,i,;perf,,,Can be used to approximate PGO-likelihood for non-loopy codes.,
Info.Inst_Mix,IpFLOP,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / #FLOP_Count,,,,,,,,Inst_Metric,Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate),< 10,4.8,Flops;InsType,,pub/v4,i,;perf,,,Reference: Tuning Performance via Metrics with Expectations,https://doi.org/10.1109/LCA.2019.2916408
Info.Inst_Mix,IpArith,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / ( #FP_Arith_Scalar + #FP_Arith_Vector ),,#NA,,1 / ( FP_Scalar + FP_Vector ),,,,Inst_Metric,Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.,< 10,4.8,Flops;InsType,,,i,,,,,
Info.Inst_Mix,IpArith_Scalar_HP,,,,,,,,,,,,INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR if #FP16 else #NA,,,,,,,,,,,,,,,,,,,,Inst_Metric,Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.,< 10,4.7,Flops;FpScalar;InsType,,,i,,,,,
Info.Inst_Mix,IpArith_Scalar_SP,,,,,,,INST_RETIRED.ANY / FP_ARITH_OPS_RETIRED.SCALAR_SINGLE,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE,,,,,,#NA,,Inst_Metric,Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.,< 10,4.7,Flops;FpScalar;InsType,,,i,,,,,
Info.Inst_Mix,IpArith_Scalar_DP,,,,,,,INST_RETIRED.ANY / FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE,,,,,,#NA,,Inst_Metric,Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.,< 10,4.7,Flops;FpScalar;InsType,,,i,,,,,
Info.Inst_Mix,IpArith_AVX128,,,,,,,INST_RETIRED.ANY / ( FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE ),,,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF ) if #FP16 else INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ),,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ),,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16 ),,,,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ),,,,,,#NA,,Inst_Metric,Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.,< 10,4.8,Flops;FpVector;InsType,,,i,,,,,
Info.Inst_Mix,IpArith_AVX256,,,,,,,INST_RETIRED.ANY / ( FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE ),,,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF ) if #FP16 else INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ),,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ),,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16 ),,,,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ),,,,,,#NA,,Inst_Metric,Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.,< 10,4.8,Flops;FpVector;InsType,,,i,,,,,
Info.Inst_Mix,IpArith_AVX512,,,,,,,,,,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF ) if #FP16 else INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ),#NA,,,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ),INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16 ),,,INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ),,,,,,,,,#NA,,Inst_Metric,Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.,< 10,4.8,Flops;FpVector;InsType,,,i,,,,,
Info.Inst_Mix,VectorMixPKI,,,,,,,,,,,,,1000 * ASSISTS.SSE_AVX_MIX / INST_RETIRED.ANY,,,,,,,,,,,,,,,,,#NA,,Inst_Metric,AVX preserve/restore assists per kilo instruction,> 0.05; $issueMV,4.6,,1,,i,,,,,
Info.Inst_Mix,IpPause,,,,,,,,,,,,,Instructions / CPU_CLK_UNHALTED.PAUSE_INST,,,,Instructions / MISC_RETIRED.PAUSE_INST,,,Instructions / ROB_MISC_EVENTS.PAUSE_INST,,,,,,,,,,,,Inst_Metric,Instructions per PAUSE (lower number means higher occurrence rate),,4.7,Flops;FpVector;InsType,,,,,,,,
Info.Inst_Mix,IpSWPF,,,,,,,INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_SWPF,,,,,,,,,,,,,,,INST_RETIRED.ANY / SW_PREFETCH_ACCESS.ANY,,,,,,,,,,Inst_Metric,Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate),< 100,4.9,Prefetches,1000,,i,,,,,
Info.Inst_Mix,Instructions,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY,INST_RETIRED.PREC_DIST,Count,Total number of retired Instructions,,4,Summary;TmaL1,,pub/v3.2,L1,;perf,,,,
Info.Pipeline,Retire,,,,,,,,,,,,,,,,,#Retired_Slots / UOPS_RETIRED.SLOTS:c1,,,,,,,,,,,,,#Retired_Slots / UOPS_RETIRED.RETIRE_SLOTS:c1,,Metric,Average number of Uops retired in cycles where at least one uop has retired.,,4.4,Pipeline;Ret,,,,,,,,
Info.Pipeline,Retire_Stall,,,,,,,UOPS_RETIRED.STALLS / CLKS,,,,,,,,,,,,,,,,,,,,,,,,,Metric,Total percent of cycles without actually retired uops,,4.4,Pipeline;Ret,,,,,,,,
Info.Pipeline,Strings_Cycles,,,,,,,,,,,,,INST_RETIRED.REP_ITERATION / UOPS_RETIRED.SLOTS:c1,,,,,,,,,,,,,,,,,,,Metric,Estimated fraction of retirement-cycles dealing with repeat instructions,> 0.1,4.4,MicroSeq;Pipeline;Ret,,,3,;EDP;perf,,,,
Info.Pipeline,IpAssist,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / ASSISTS.ANY,,,,,INST_RETIRED.ANY / ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ),,,,,,,,,,Inst_Metric,Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate),< 100000,4.6,MicroSeq;Pipeline;Ret;Retire,,pub/v4.6,,,,,,
Info.Pipeline,Execute,,,,,,,#NA,,,,,,,,,,,,,,,,,UOPS_EXECUTED.THREAD / #Execute_Cycles,,#NA,,UOPS_EXECUTED.THREAD / #Execute_Cycles,,,,Metric,Instruction-Level-Parallelism (average number of uops executed when there is execution) per physical core,,4.7,Cor;Pipeline;PortsUtil;SMT,#Exe_Ports,,i,,,,,
Info.Pipeline,Fetch_LSD,,,,,,#NA,,#NA,,,,#NA,,,,#NA,,,#NA,LSD.UOPS / LSD.CYCLES_ACTIVE,,,,,,,,,,#NA,,Metric,Average number of uops fetched from LSD per cycle,,5.02,Fed;FetchBW,,,,,,,,
Info.Pipeline,Fetch_DSB,,,,,,,,,,,,,,,,,,,,,,IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY,,,,,,,,,,Metric,Average number of uops fetched from DSB per cycle,,4.8,Fed;FetchBW,,,,,,,,
Info.Pipeline,Fetch_MITE,,,,,,,,,,,,,,,,,IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY,,,,,IDQ.MITE_UOPS / IDQ.MITE_CYCLES,,,,,,,,,,Metric,Average number of uops fetched from MITE per cycle,,4.8,Fed;FetchBW,,,,,,,,
Info.Pipeline,Fetch_MS,,,,,,,IDQ.MS_UOPS / IDQ.MS_UOPS:c1,,,,,,#NA,,,,,,,,,IDQ.MS_UOPS / IDQ.MS_UOPS:c1,,,,,,,,,,Metric,Average number of uops fetched from MS per cycle,,5.1,Fed;FetchLat;MicroSeq,,,,,,,,
Info.Frontend,Fetch_UpC,,,,,,,,,,,,,,,,,,,,,,UOPS_ISSUED.ANY / UOPS_ISSUED.ANY:c1,,,,,,,,,,Metric,Average number of Uops issued by front-end when it issued something,,4.3,Fed;FetchBW,6,pub/v4.5,,,,,,
Info.Frontend,LSD_Coverage,,,,,,#NA,,#NA,,,,#NA,,,,#NA,,,#NA,LSD.UOPS / #Fetched_Uops,,,,,,,,,,#NA,,Metric,Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache),,5.02,Fed;LSD,1,pub/v4,i,;perf,,,,
Info.Frontend,DSB_Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,IDQ.DSB_UOPS / #Fetched_Uops,,Metric,Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache),< 0.7 & #HighIPC; $issueFB,4.5,DSB;Fed;FetchBW,1,pub/v3,i,;perf;vtune,,,See section 'Decoded ICache' in Optimization Manual,http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
Info.Frontend,Unknown_Branch_Cost,,,,,,,,,,,,,INT_MISC.UNKNOWN_BRANCH_CYCLES / INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1,,,,,,,,,,,,,,,,,,,Metric,Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.,,4.6,Fed,,,,,,,,
Info.Frontend,DSB_Switch_Cost,,,,,,,,,,,,,,,,,DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1,,,,,DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT,,,,,,,,,,Metric,Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.,,4.4,DSBmiss,,,,,,,,
Info.Frontend,TBpC,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,BR_INST_RETIRED.NEAR_TAKEN / CLKS,,Metric,Taken Branches retired Per Cycle,,5,Branches;FetchBW,,,,,,,,
Info.Botlnk.L2,DSB_Misses,,,,,,,,,,,,,,,,,,,,,,100 * ( Fetch_Latency * DSB_Switches / ##Fetch_Latency + Fetch_Bandwidth * MITE / ##Fetch_Bandwidth ),,,,,,,,,,Scaled_Slots,Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.,> 10; $issueFB,4.5,DSBmiss;Fed,,pub/v4.3,0,;EDP;perf;VTune,,InTree,,
Info.Botlnk.L2,DSB_Bandwidth,,,,,,,,,,,,,,,,,,,,,,100 * ( Frontend_Bound * ( Fetch_Bandwidth / ##Frontend_Bound ) * ( DSB / ##Fetch_Bandwidth ) ),,,,,,,,,,Scaled_Slots,Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck.,> 10; $issueFB,4.8,DSB;Fed;FetchBW,,,0,;EDP;perf;VTune,,InTree,,
Info.Frontend,DSB_Switches_Ret,,,,,,,,,FRONTEND_RETIRED.ANY_DSB_MISS*$PEBS / CLKS,,,,,,,,,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU retirement was stalled likely due to retired DSB misses,> 0.05,5,DSBmiss;Fed;FetchLat,,,3,,,,,
Info.Frontend,MS_Latency_Ret,,,,,,,,,FRONTEND_RETIRED.MS_FLOWS*$PEBS / CLKS,,,,,,,,,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU retirement was stalled likely due to retired operations that invoke the Microcode Sequencer,> 0.05,5,Fed;FetchLat;MicroSeq,,,3,,,,,
Info.Frontend,Unknown_Branches_Ret,,,,,,,,,FRONTEND_RETIRED.UNKNOWN_BRANCH*$PEBS / CLKS,,,,,,,,,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU retirement was stalled likely due to retired branches who got branch address clears,,5,Fed;FetchLat,,,3,,,,,
Info.Frontend,ICache_Miss_Latency,,,,,,,,,ICACHE_DATA.STALLS / ICACHE_DATA.STALL_PERIODS,,,,ICACHE_DATA.STALLS / ICACHE_DATA.STALLS:c1:e1,,,,ICACHE_16B.IFDATA_STALL / ICACHE_16B.IFDATA_STALL:c1:e1,,,,,ICACHE_16B.IFDATA_STALL / ICACHE_16B.IFDATA_STALL:c1:e1  + 2,,,,,,,,,,Metric,Average Latency for L1 instruction cache misses,,4.5,Fed;FetchLat;IcMiss,,,3,,,,,
Info.Botlnk.L2,IC_Misses,,,,,,,,,,,,,,,,,,,,,,100 * ( Fetch_Latency * ICache_Misses / ##Fetch_Latency ),,,,,,,,,,Scaled_Slots,Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.,> 5; $issueFL,4.5,Fed;FetchLat;IcMiss,,,0,,,InTree,,
Info.Frontend,IpDSB_Miss_Ret,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS,,,,,,,,,,Inst_Metric,Instructions per non-speculative DSB miss (lower number means higher occurrence rate),< 50,4.3,DSBmiss;Fed,,,3,;EDP;perf,,,,
Info.Frontend,IpUnknown_Branch,,,,,,,,,,,,,,,,,,,,,,,,,,,,Instructions / BACLEARS.ANY,,,,Metric,Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate),,4.5,Fed,,,i,EDP,,,,
Info.Frontend,L2MPKI_Code,,,,,,,,,,,,,,,,,,,,,,1000 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY,,,,,,,,,,Metric,L2 cache true code cacheline misses per kilo instruction ,,4.5,IcMiss,,,i,,,,,
Info.Frontend,L2MPKI_Code_All,,,,,,,,,,,,,,,,,,,,,,1000 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY,,,,,,,,,,Metric,L2 cache speculative code cacheline misses per kilo instruction ,,4.5,IcMiss,,,i,,,,,
Info.Bad_Spec,IpMispredict,,,,,,,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES,,,,Inst_Metric,Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate),< 200,4.4,Bad;BadSpec;BrMispredicts,,pub/v3.4,i,;perf,,,,
Info.Bad_Spec,IpMisp_Cond_Ntaken,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN,,,,,,,,,,,,,,,Inst_Metric,Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher occurrence rate).,< 200,4.5,Bad;BrMispredicts,,,,,,,,
Info.Bad_Spec,IpMisp_Cond_Taken,,,,,,,#NA,,,,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN,,,,,,,,,,,,,,,Inst_Metric,Instructions per retired Mispredicts for conditional taken branches (lower number means higher occurrence rate).,< 200,4.5,Bad;BrMispredicts,,,,,,,,
Info.Bad_Spec,IpMisp_Cond_Taken_Bwd,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN_BWD,,,,,,,,,,,,,,,,,,,,,,,,,,Instructions per retired Mispredicts for conditional backward-taken branches (lower number means higher occurrence rate).,,5.1,Bad;BrMispredicts,,,,,,,,
Info.Bad_Spec,IpMisp_Cond_Taken_Fwd,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN_FWD,,,,,,,,,,,,,,,,,,,,,,,,,,Instructions per retired Mispredicts for conditional forward-taken branches (lower number means higher occurrence rate).,,5.1,Bad;BrMispredicts,,,,,,,,
Info.Bad_Spec,IpMisp_Ret,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.RET,,,,,,,,,,,,,,,Inst_Metric,Instructions per retired Mispredicts for return branches (lower number means higher occurrence rate).,< 500,4.5,Bad;BrMispredicts,,,,,,,,
Info.Bad_Spec,IpMisp_Indirect,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT,,,,,,,,,,,Instructions / ( #Retire_Fraction * BR_MISP_EXEC.INDIRECT ),,,,Inst_Metric,Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).,< 1000,4.6,Bad;BrMispredicts,,,i,,,,,
Info.Bad_Spec,Branch_Misprediction_Cost,,,,,,,,,,,,,,,,,,,,,,Mispredictions * SLOTS / #Pipeline_Width / BR_MISP_RETIRED.ALL_BRANCHES / 100,,,,,,,,#NA,,Core_Metric,Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear),; $issueBM,5.02,Bad;BrMispredicts,50,pub/v3.4,i,;bot;perf,,,,
Info.Bad_Spec,Spec_Clears_Ratio,,,,,,,,,,,,,,,,,,,,,,INT_MISC.CLEARS_COUNT / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ),,,,,,,,,,Metric,Speculative to Retired ratio of all clears (covering Mispredicts and nukes),,4.6,BrMispredicts,,,,,,,,
Info.Branches,Cond_NT,,,,,,,,,,,,,,,,,BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES,,,,,BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES,,,,,,,,,,Fraction,Fraction of branches that are non-taken conditionals,,4.3,Bad;Branches;CodeGen;PGO,1,,i,,,,,
Info.Branches,Cond_TK,,,,,,,#NA,,,,,,,,,,BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES,,,,,( BR_INST_RETIRED.CONDITIONAL_PS - BR_INST_RETIRED.NOT_TAKEN )  / BR_INST_RETIRED.ALL_BRANCHES,,,,,,,,,,Fraction,Fraction of branches that are taken conditionals,,4.3,Bad;Branches;CodeGen;PGO,1,,i,,,,,
Info.Branches,Cond_TK_Bwd,,,,,,,BR_INST_RETIRED.COND_TAKEN_BWD / BR_INST_RETIRED.ALL_BRANCHES,,,,,,,,,,,,,,,,,,,,,,,,,Fraction,Fraction of branches that are forward taken conditionals,> 0.3,5,Bad;Branches;CodeGen;PGO,1,,,,,,,
Info.Branches,Cond_TK_Fwd,,,,,,,BR_INST_RETIRED.COND_TAKEN_FWD / BR_INST_RETIRED.ALL_BRANCHES,,,,,,,,,,,,,,,,,,,,,,,,,Fraction,Fraction of branches that are forward taken conditionals,> 0.2,5.02,Bad;Branches;CodeGen;PGO,1,,,,,,,
Info.Branches,CallRet,,,,,,,,,,,,,,,,,,,,,,( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES,,,,,,,,,,Fraction,Fraction of branches that are CALL or RET,,4.3,Bad;Branches,1,,i,,,,,
Info.Branches,Jump,,,,,,,,,,,,,,,,,,,,,,#Br_DoI_Jumps / BR_INST_RETIRED.ALL_BRANCHES,,,,,,,,,,Fraction,Fraction of branches that are unconditional (direct or indirect) jumps,,5.1,Bad;Branches,1,,i,,,,,
Info.Branches,Other_Branches,,,,,,,1 - ( Cond_NT + Cond_TK_Bwd + Cond_TK_Fwd + CallRet + Jump ),,,,,,,,,,1 - ( Cond_NT + Cond_TK + CallRet + Jump ),,,,,,,,,,,,,,,Fraction,Fraction of branches of other types (not individually covered by other metrics in Info.Branches group),,4.3,Bad;Branches,1,,i,,,,,
Info.Memory,Load_Miss_Real_Latency,,,,,,,L1D_PENDING.LOAD / L1D_MISS.LOAD,,,,,,L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY,,,,,,,,,L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS_PS + MEM_LOAD_RETIRED.FB_HIT_PS ),,,,,,L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS ),,#NA,,Clocks_Latency,Actual Average Latency for L1 data-cache miss demand load operations (in core cycles),,4.4,Mem;MemoryBound;MemoryLat,1000,pub/v3.1,3,;bot;EDP;perf;VTune,,,,
Info.Memory,MLP,,,,,,,L1D_PENDING.LOAD / L1D_PENDING.LOAD_CYCLES,,,,,,,,,,,,,,,,,,,,,L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES,,#NA,,Metric,Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor),,3.4,Mem;MemoryBound;MemoryBW,10,pub/v3.3,i,;EDP;perf,,,,
Info.Memory,L1DL0_MPKI,,,,,,,1000 * ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.L1_HIT_L1 ) / INST_RETIRED.ANY,,,,,,,,,,,,,,,,,,,,,,,#NA,,Metric,L0 cache true misses per kilo instruction for retired demand loads,,5.1,CacheHits;Mem,,,,,,,,
Info.Memory,L1MPKI,,,,,,,,,,,,,,,,,,,,,,1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY,,,,,,1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY,,#NA,,Metric,L1 cache true misses per kilo instruction for retired demand loads,,3.3,CacheHits;Mem,,pub/v3.3,i,;perf,,,,
Info.Memory,L2MPKI,,,,,,,,,,,,,,,,,,,,,,1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY,,,,,,1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY,,#NA,,Metric,L2 cache true misses per kilo instruction for retired demand loads,,3.3,Mem;Backend;CacheHits,,pub/v3.3,i,;perf,,,,
Info.Memory,L3MPKI,,,,,,,,,,,,,,,,,,,,,,1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY,,,,1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS_PS / INST_RETIRED.ANY,,1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS / INST_RETIRED.ANY,,#NA,,Metric,L3 cache true misses per kilo instruction for retired demand loads,,3.3,Mem;,,pub/v3.3,i,;perf,,,,
Info.Memory,FB_HPKI,,,,,,,,,,,,,,,,,,,,,,1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY,,,,,,,,#NA,,Metric,Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries),,4.4,CacheHits;Mem,,,i,,,,,
Info.Memory,L1MPKI_Load,,,,,,,,,,,,,,,,,,,,,,1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY,,,,,,,,#NA,,Metric,L1 cache true misses per kilo instruction for all demand loads (including speculative),,4.1,CacheHits;Mem,,,i,,,,,
Info.Memory,L2MPKI_All,,,,,,,,,,,,,,,1000 * L2_RQSTS.MISS / INST_RETIRED.ANY,,1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / Instructions,,,,,,,1000 * L2_RQSTS.MISS / INST_RETIRED.ANY,,,,,,#NA,,Metric,L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative),,4.4,CacheHits;Mem;Offcore,,pub/v3.5,i,;perf,,,,
Info.Memory,L2MPKI_Load,,,,,,,,,,,,,,,,,,,,,,,,1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY,,,,,,#NA,,Metric,L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative),,4.4,CacheHits;Mem,,,i,;,,,,
Info.Memory,L2MPKI_RFO,,,,,,,,,,,,,,,,,1000 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY,,,,,,,,,,,1000 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.ANY,,#NA,,Metric,Offcore requests (L2 cache miss) per kilo instruction for demand RFOs,,4.8,CacheMisses;Offcore,,,i,,,,,
Info.Memory,L2HPKI_All,,,,,,,,,,,,,,,1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY,,#NA,,,,,,,1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY,,,,,,#NA,,Metric,L2 cache hits per kilo instruction for all request types (including speculative),,4.1,CacheHits;Mem,,pub/v3.5,i,;perf,,,,
Info.Memory,L2HPKI_Load,,,,,,,,,,,,,,,,,,,,,,,,1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY,,,,,,#NA,,Metric,L2 cache hits per kilo instruction for all demand loads  (including speculative),,3.5,CacheHits;Mem,,,i,;,,,,
Info.Memory,L1DL0_Cache_Fill_BW,,,,,,,64 * L1D.L0_REPLACEMENT / #OneBillion / Time,,,,,,,,,,,,,,,,,,,,,,,#NA,,Metric,Average per-thread data fill bandwidth to the Level 0 within L1D cache [GB / sec],,5,Mem;MemoryBW,,,,,,,,
Info.Memory,L1D_Cache_Fill_BW,,,,,,,64 * L1D.L1_REPLACEMENT / #OneBillion / Time,,,,,,,,,,,,,,,,,,,,,64 * L1D.REPLACEMENT / #OneBillion / Time,,#NA,,Metric,Average per-thread data fill bandwidth to the L1 data cache [GB / sec],,4.6,Mem;MemoryBW,,pub/v4.6,i,;perf,,,,
Info.Memory,L2_Cache_Fill_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,64 * L2_LINES_IN.ALL / #OneBillion / Time,,#NA,,Metric,Average per-thread data fill bandwidth to the L2 cache [GB / sec],,4.6,Mem;MemoryBW,,pub/v4.6,i,;perf,,,,
Info.Memory,L3_Cache_Fill_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,64 * LONGEST_LAT_CACHE.MISS / #OneBillion / Time,,#NA,,Metric,Average per-thread data fill bandwidth to the L3 cache [GB / sec],,4.6,Mem;MemoryBW,,pub/v4.6,i,;perf,,,,
Info.Memory,L3_Cache_Access_BW,,,,,,,,,,,,,,,,,,,,,,64 * OFFCORE_REQUESTS.ALL_REQUESTS / #OneBillion / Time,,,,,,,,#NA,,Metric,Average per-thread data access bandwidth to the L3 cache [GB / sec],,4.6,Mem;MemoryBW;Offcore,,pub/v4.6,i,;perf,,,,
Info.Memory.TLB,Page_Walks_Utilization,,,,,,,( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * CLKS ),,,,,,( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * CORE_CLKS ),,,,( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CORE_CLKS ),,,,,( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CORE_CLKS ),( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * CORE_CLKS ),( ITLB_MISSES.WALK_DURATION:c1 + DTLB_LOAD_MISSES.WALK_DURATION:c1 + DTLB_STORE_MISSES.WALK_DURATION:c1 + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CORE_CLKS,,,,( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CORE_CLKS,,#NA,,Core_Metric,Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses,> 0.5,4.3,Mem;MemoryTLB,1,pub/v3.2,i,;perf,,,,
Info.Memory.TLB,Code_STLB_MPKI,,,,,,,,,,,,,,,,,,,,,,1000 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY,,,,,,,,,,Metric,STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk),,4.5,Fed;MemoryTLB,,,,,,,,
Info.Memory.TLB,Load_STLB_MPKI,,,,,,,,,,,,,,,,,,,,,,1000 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY,,,,,,,,,,Metric,STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk),,4.5,Mem;MemoryTLB,,,,,,,,
Info.Memory.TLB,Store_STLB_MPKI,,,,,,,,,,,,,,,,,,,,,,1000 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY,,,,,,,,,,Metric,STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk),,4.5,Mem;MemoryTLB,,,,,,,,
Info.Memory.TLB,Load_STLB_Miss_Ret,,,,,,,,,MEM_INST_RETIRED.STLB_MISS_LOADS*$PEBS / CLKS,,,,,,,,,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand loads,> 0.05,5,Mem;MemoryTLB,,,3,,,,,
Info.Memory.TLB,Store_STLB_Miss_Ret,,,,,,,,,MEM_INST_RETIRED.STLB_MISS_STORES*$PEBS / CLKS,,,,,,,,,,,,,,,,,,,,,,,Clocks_Retired,This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores,> 0.05,5,Mem;MemoryTLB,,,3,,,,,
Info.Memory.Core,L1D_Cache_Fill_BW_2T,,,,,,,#NA,,,,,,,,,,,,,,,,,,,,,L1D_Cache_Fill_BW,,#NA,,Core_Metric,Average per-core data fill bandwidth to the L1 data cache [GB / sec],,4.6,Mem;MemoryBW,,,i,,,,,
Info.Memory.Core,L2_Cache_Fill_BW_2T,,,,,,,#NA,,,,,,,,,,,,,,,,,,,,,L2_Cache_Fill_BW,,#NA,,Core_Metric,Average per-core data fill bandwidth to the L2 cache [GB / sec],,4.6,Mem;MemoryBW,,,i,,,,,
Info.Memory.Core,L3_Cache_Fill_BW_2T,,,,,,,#NA,,,,,,,,,,,,,,,,,,,,,L3_Cache_Fill_BW,,#NA,,Core_Metric,Average per-core data fill bandwidth to the L3 cache [GB / sec],,4.6,Mem;MemoryBW,,,i,,,,,
Info.Memory.Core,L3_Cache_Access_BW_2T,,,,,,,#NA,,,,,,,,,,,,,,,L3_Cache_Access_BW,,,,,,,,#NA,,Core_Metric,Average per-core data access bandwidth to the L3 cache [GB / sec],,4.7,Mem;MemoryBW;Offcore,,,i,,,,,
Info.Memory.Core,L2_Evictions_Silent_PKI,,,,,,,,,,,,,,,,,,,,,1000 * L2_LINES_OUT.SILENT / Instructions,,,,,,,,,#NA,,Core_Metric,Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory),,4.4,L2Evicts;Mem;Server,,pub/v3.6,i,;perf,,,,
Info.Memory.Core,L2_Evictions_NonSilent_PKI,,,,,,,,,,,,,,,,,,,,,1000 * L2_LINES_OUT.NON_SILENT / Instructions,,,,,,,,,#NA,,Core_Metric,Rate of non silent evictions from the L2 cache per Kilo instruction,,4.4,L2Evicts;Mem;Server,,pub/v3.6,i,;perf,,,,
Info.Memory.Prefetches,Useless_HWPF,,,,,,,,,,,,,,,,,L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT ),,,,,,,,,,,,,#NA,,Metric,Rate of L2 HW prefetched lines that were not used by demand accesses,> 0.15,5,Prefetches,1,,,,,,,
Info.Memory.Latency,Load_L2_Miss_Latency,,,,,,,,,,,,,,,,,,,,,,,,,,,,OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD,,,,Clocks_Latency,Average Latency for L2 cache miss demand Loads,,4.5,LockCont;Memory_Lat;Offcore,1000,,,;EDP,,,,
Info.Memory.Latency,Load_L3_Miss_Latency,,,,,,,,,,,,,OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD,,,,,,,,,,,,,,,,,,,Clocks_Latency,Average Latency for L3 cache miss demand Loads,,4.5,Memory_Lat;Offcore,1000,,,;EDP,,,,
Info.Memory.Latency,Load_L2_MLP,,,,,,,,,,,,,,,,,OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1,,,,,,,,,,,OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD,,,,Metric,Average Parallel L2 cache miss demand Loads,,4.5,Memory_BW;Offcore,100,,,,,,,
Info.Memory.Latency,Data_L2_MLP,,,,,,,,,,,,,OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD,,,,,,,,,,,,,,,OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD,,,,Metric,Average Parallel L2 cache miss data reads,,4.6,Memory_BW;Offcore,100,,,,,,,
Info.Memory.Mix,Offcore_Read_Any_PKI,,,,,,,,,,,,1000 * OCR.READS_TO_CORE.ANY_RESPONSE / Instructions,,,,,,,,,,,,,,,,,,#NA,,Metric,Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches),,4.6,CacheHits;Offcore;Server,,,,,,,,
Info.Memory.Mix,Offcore_Read_L3M_PKI,,,,,,,,,,,,1000 * OCR.READS_TO_CORE.L3_MISS / Instructions,,,,,,,,,,,,,,,,,,#NA,,Metric,L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches),,4.6,Offcore;Server,,,,,,,,
Info.Memory.Mix,Offcore_Read_HBM_PKI,,,,,,,,,,#NA,#NA if #Memory > 2 else 1000 * OCR.DEMAND_DATA_RD.PMM / Instructions,,,,,,,,,,,,,,,,,,,#NA,,Metric,High-Bandwidth Memory (HBM) accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches),,4.7,Offcore;Server,,,,,,,,
Info.Memory.Mix,Offcore_MWrite_Any_PKI,,,,,,,,,,,,1000 * OCR.MODIFIED_WRITE.ANY_RESPONSE / Instructions,,,,,,,,,,,,,,,,,,#NA,,Metric,Off-core accesses per kilo instruction for modified write requests,,4.6,Offcore;Server,,,,,,,,
Info.Memory.Mix,UC_Load_PKI,,,,,,,,,,,,,,,,,,,,,,1000 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY,,,,,,,,,,Metric,Un-cacheable retired load per kilo instruction,,4.6,Mem,,,,;EDP;perf,,,,
Info.Memory.Mix,Bus_Lock_PKI,,,,,,,,,,,,,,,,,1000 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY,,,,,,,,,,,,,,,Metric,"""Bus lock"" per kilo instruction",,4.6,Mem,,,,;EDP;perf,,,,
Info.System,CPU_Utilization,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,CPUs_Utilized / Num_CPUs,,Metric,Average CPU Utilization (percentage),,4.8,HPC;Summary,1,pub/v3,i,perf,,,,
Info.System,CPUs_Utilized,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,CPU_CLK_UNHALTED.REF_TSC / TSC,,Metric,Average number of utilized CPUs,,4.8,Summary,300,pub/v4.6,,;bot;EDP;perf,,,,
Info.System,Core_Frequency,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Turbo_Utilization * TSC / #OneBillion / Time,,System_Metric,Measured Average Core Frequency for unhalted processors [GHz],,4.6,Summary;Power,,pub/v3.4,i,;bot;EDP;perf;VTune,,,,
Info.System,GFLOPs,,,,,,,,,,,,,,,,,,,,,,,,( #FLOP_Count / #OneBillion ) / Time,,#NA,,,,( #FLOP_Count / #OneBillion ) / Time,,Metric,"Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width",,4.8,Cor;Flops;HPC,200,pub/v3,i,;EDP;perf,,,,
Info.System,Turbo_Utilization,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,CLKS / CPU_CLK_UNHALTED.REF_TSC,,Core_Metric,Average Frequency Utilization relative nominal frequency,,3,Power,10,pub/v3,i,;bot;EDP;perf;VTune,,,,
Info.System  ,SMT_2T_Utilization,,,,,,,#NA,,,,,,,,,,1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0,,,,,,,,,,,,,1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0,,Core_Metric,Fraction of cycles where both hardware Logical Processors were active,,4.1,SMT,1,pub/v3,i,;EDP,,,,
Info.System,Kernel_Utilization,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD_P:SUP / CPU_CLK_UNHALTED.THREAD,,Metric,Fraction of cycles spent in the Operating System (OS) Kernel mode,> 0.05,4.2,OS,1,pub/v3,i,;perf,,,,
Info.System,Kernel_CPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD_P:SUP / INST_RETIRED.ANY_P:SUP,,Metric,Cycles Per Instruction for the Operating System (OS) Kernel mode,,4.3,OS,,pub/v4.3,i,;perf,,,,
Info.System,C0_Wait,,,,,,,,,,,,,CPU_CLK_UNHALTED.C0_WAIT / CLKS,,,,,,,,,,,,,,,,,,,Metric,"Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states",> 0.05,4.6,C0Wait,1,,i,;EDP;perf,,ZeroOk,Sample code of TPAUSE: https://github.com/torvalds/linux/blob/master/arch/x86/lib/delay.c#L105,"If running on Linux, please check the power control interface: https://github.com/torvalds/linux/blob/master/arch/x86/kernel/cpu/umwait.c and https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-devices-system-cpu#L587"
Info.System,DRAM_BW_Use,,,,,,,,( 64 * ( UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD + UNC_M_CAS_COUNT_SCH0.WR +  UNC_M_CAS_COUNT_SCH1.WR ) / #OneBillion ) / Time,32 * UNC_M_TOTAL_DATA / #OneBillion / Time,,,,,,,,,,,,,,,,,,,,( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / #OneBillion ) / Time,64 * ( UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL ) / #OneMillion / Time / 1000,,GB/sec,Average external Memory Bandwidth Use for reads and writes [GB / sec],; $issueBW,5.2,HPC;MemOffcore;MemoryBW;SoC,200,pub/v3,i,;perf,,,,
Info.Memory.SoC,R2C_Offcore_BW,,,,,,,,,,,,64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / Time,,,,,,,,,,,,,,,,,,,,GB/sec,Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.,,5.1,HPC;Mem;MemoryBW;Server;Offcore,,,,;EDP;perf,,,,
Info.Memory.SoC,R2C_L3M_BW,,,,,,,,,,,,64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / Time,,,,,,,,,,,,,,,,,,,,GB/sec,Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.,,5.1,HPC;Mem;MemoryBW;Server;Offcore,,,,;EDP;perf,,,,
Info.Memory.SoC,R2C_DRAM_BW,,,,,,,,,,,,64 * OCR.READS_TO_CORE.DRAM / 1e9 / Time,,,,,,,,,,,,,,,,,,,,GB/sec,Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.,,5.1,HPC;Mem;MemoryBW;Server;Offcore,,,,;EDP;perf,,,,
Info.Memory.SoC,R2C_HBM_BW,,,,,,,,,,#NA,#NA if #Memory > 2 else 64 * OCR.DEMAND_DATA_RD.PMM / 1e9 / Time,,,,,,,,,,,,,,,,,,,,,GB/sec,Average HBM BW for Reads-to-Core. See R2C_Offcore_BW.,,5.1,HPC;Mem;MemoryBW;Server;Offcore,,,,;EDP;perf,,,,
Info.System,MEM_Read_Latency,,,,,,,,,#NA,,,#OneBillion * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( Socket_CLKS / Time ),,,( UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD ) / UNC_ARB_TRK_REQUESTS.RD,#OneBillion * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( Socket_CLKS / Time ),#NA,,,,#OneBillion * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( Socket_CLKS / Time ),#OneBillion * ( UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ ) / ( Socket_CLKS / Time ),,,#OneBillion * ( UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182 / UNC_C_TOR_INSERTS.MISS_OPCODE:opc=0x182 ) / ( Socket_CLKS / Time ),,,,"#OneBillion * ( ""UNC_C_TOR_OCCUPANCY.MISS_OPCODE/Match=0x182"" / ""UNC_C_TOR_INSERTS.MISS_OPCODE/Match=0x182"" ) / ( Socket_CLKS / Time )",#NA,,NanoSeconds,Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only),,4.5,Mem;MemoryLat;SoC,1000,pub/v3.4,i,;perf,,,,
Info.System,MEM_Parallel_Reads,,,,,,,#NA,,,,,UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1,,,UNC_ARB_DAT_OCCUPANCY.RD / UNC_ARB_DAT_OCCUPANCY.RD:c1,UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1,#NA,,,,UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1,UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ:c1,,,UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182 / UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182:c1,,,,"""UNC_C_TOR_OCCUPANCY.MISS_OPCODE/Match=0x182"" / ""UNC_C_TOR_OCCUPANCY.MISS_OPCODE/Match=0x182:c1""",#NA,,System_Metric,Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches,,4.5,Mem;MemoryBW;SoC,100,pub/v3.4,i,;perf,,,,
Info.System,MEM_PMM_Read_Latency,,,,,,,,,,,#NA,,,,,( #OneBillion * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / UNC_CHA_CLOCKTICKS:one_unit ) if #PMM_App_Direct else #NA,,,( #OneBillion * ( UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS ) / UNC_M_CLOCKTICKS:one_unit ) if #PMM_App_Direct else #NA,,,,,,,,,,,#NA,,NanoSeconds,Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches,,4.6,MemOffcore;MemoryLat;SoC;Server,,pub/v3.5,i,;perf,,,,
Info.System,MEM_DRAM_Read_Latency,,,,,,,,,,,,,,,,#OneBillion * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / UNC_CHA_CLOCKTICKS:one_unit,,,,,#OneBillion * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS ) / UNC_M_CLOCKTICKS:one_unit,,,,,,,,,#NA,,NanoSeconds,Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches,,4.6,MemOffcore;MemoryLat;SoC;Server,,,i,;,,,,
Info.System,CXL_Mem_Read_BW,,,,,,,,( ( 64 * UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA / #OneBillion ) / Time ) if #PMM_App_Direct else #NA,,,,,,,,,,,( ( 64 * UNC_M_PMM_RPQ_INSERTS / #OneBillion ) / Time ) if #PMM_App_Direct else #NA,,,,,,,,,,,#NA,,GB/sec,Average 3DXP Memory Bandwidth Use for reads [GB / sec],,4.6,MemOffcore;MemoryBW;SoC;Server,,pub/v3.5,i,;perf,,,,
Info.System,CXL_Mem_Write_BW,,,,,,,,( ( 64 * UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA / #OneBillion ) / Time ) if #PMM_App_Direct else #NA,,,,,,,,,,,( ( 64 * UNC_M_PMM_WPQ_INSERTS / #OneBillion ) / Time ) if #PMM_App_Direct else #NA,,,,,,,,,,,#NA,,GB/sec,Average 3DXP Memory Bandwidth Use for Writes [GB / sec],,4.6,MemOffcore;MemoryBW;SoC;Server,,pub/v3.5,i,;perf,,,,
Info.System,IO_Read_BW,,,,,,,,,,,,,,,,UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / #OneBillion / Time,,,,,( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / #OneBillion / Time,,,,,,,,,,,GB/sec,Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU,,4.6,IoBW;MemOffcore;SoC;Server,,pub/v4,i,;perf,,,,
Info.System,IO_Write_BW,,,,,,,,,,,,( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / #OneBillion / Time,,,,( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / #OneBillion / Time,,,,,( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / #OneBillion / Time,,,,,,,,,,,GB/sec,Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU,,4.6,IoBW;MemOffcore;SoC;Server,,pub/v4,i,;perf,,,,
Info.System,UPI_Data_Transmit_BW,,,,,,,,,,,,UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1000000,,,,,,,,,,,,,,,,,,,,MB/sec,Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec],,4.5,SoC;Server,,,,;EDP,,,,
Info.System,Power,,,,,,,,,,,,,,,,,,,,,,,,,( FREERUN_PKG_ENERGY_STATUS * #Energy_Unit + 15.6 * FREERUN_DRAM_ENERGY_STATUS ) / ( #DurationTimeInSeconds * #OneMillion ),UNC_PKG_ENERGY_STATUS * #Energy_Unit / ( Time * #OneMillion ),( FREERUN_PKG_ENERGY_STATUS + FREERUN_DRAM_ENERGY_STATUS ) * #Energy_Unit / ( #DurationTimeInSeconds * #OneMillion ),UNC_PKG_ENERGY_STATUS * #Energy_Unit / ( Time * #OneMillion ),,#NA,,System_Metric,Total package Power in Watts,,2.9,Power;SoC,200,pub/v3.2,i,;,,,,
Info.System,Time,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,#DurationTimeInSeconds,,Seconds,Run duration time in seconds,< 1,4,Summary,,pub/v3,i,;bot;EDP;perf;VTune,,,,
Info.System,MUX,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD,,Clocks,PerfMon Event Multiplexing accuracy indicator,( > 1.1 | < 0.9 ),3.1,Summary,,pub/v3,i,;,,,,
Info.System,Socket_CLKS,,,,,,,,,,,,,,,,,,,,,UNC_CHA_CLOCKTICKS:one_unit,,,,,,,,UNC_C_CLOCKTICKS:one_unit,UNC_CLOCK.SOCKET,,Count,Socket actual clocks when any core is active on that socket,,3.4,SoC,,pub/v3,i,;perf,,,,
Info.System,IpFarBranch,,,,,,,,,,,,,,,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:USER,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH_PS:USER,,Inst_Metric,"Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",< 1000000,4.3,Branches;OS,,pub/v3.6,i,;perf,,,,
.,auxiliary,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,-,-,,2.5,,,pub/v3,-,;bot;,,,,
Aux,#Backend_Bound_Cycles,,,,,,,,,,,,,#NA,,,,CYCLE_ACTIVITY.STALLS_TOTAL + #Few_Uops_Executed_Threshold + EXE_ACTIVITY.BOUND_ON_STORES,,,,,CYCLE_ACTIVITY.STALLS_TOTAL + #Few_Uops_Executed_Threshold + EXE_ACTIVITY.BOUND_ON_STORES,,( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + ( UOPS_EXECUTED.CORE:c1 - #Few_Uops_Executed_Threshold ) / 2 - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ) if #SMT_on else ( #STALLS_TOTAL + UOPS_EXECUTED.CORE:c1 - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + UOPS_DISPATCHED.THREAD:c1 - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,Count,,,4.4,,,pub,2,;bot;,,,,
Aux,#Br_DoI_Jumps,,,,,,,BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN_BWD - BR_INST_RETIRED.COND_TAKEN_FWD - 2 * BR_INST_RETIRED.NEAR_CALL,,,,,,,,,,BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL,,,,,BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.COND_PS - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL,,,,,,,,,,Count,,,5.02,Branches,,,0,,,,,
Aux,#Branching_Retired,,,,,,,,,,,,,,,,,,,,,,( BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP ) / SLOTS,,,,,,,,#NA,,Slots,,,4.8,BvBO;Ret,,pub/5.0,0,;bot;,,,,
Aux,#Serialize_Core,,,,,,,,,,,,,Core_Bound * ( Serializing_Operation + RS.EMPTY_RESOURCE / CLKS * Ports_Utilized_0 ) / ##Core_Bound,,,,,,,,,Core_Bound * ( Serializing_Operation + Core_Bound * RS_EVENTS.EMPTY_CYCLES / CLKS * Ports_Utilized_0 ) / ##Core_Bound,,,,,,,,,,Fraction,,,4.9,,,pub/5.0,0,;bot;,,,,
Aux,#Umisp,,,,,,,,,,,,,,,,,,,,,,10 * Microcode_Sequencer * Other_Mispredicts / Branch_Mispredicts,,,,,,,,,,Fraction,,,4.7,MS,,pub/v4.6,0,;bot;,,,,
Aux,#Assist,,,,,,,"( Microcode_Sequencer / ( Microcode_Sequencer + max( 0 , Heavy_Operations - Microcode_Sequencer ) ) ) * ( #Avg_Assist_Cost * ASSISTS.ANY / SLOTS / Microcode_Sequencer )",,,,,,,,,,,,,,,( Microcode_Sequencer / ##Heavy_Operations ) * ( Assists / Microcode_Sequencer ),,,,,,,,,,Fraction,,,4.6,MS,,pub/v4.6,0,;bot;,,,,
Aux,#Assist_Frontend,,,,,,,,,,,,,( 1 - INST_RETIRED.REP_ITERATION / UOPS_RETIRED.MS:c1 ) * ( Fetch_Latency * ( MS_Switches + Branch_Resteers * ( Clears_Resteers + Mispredicts_Resteers * Other_Mispredicts / Branch_Mispredicts ) / ##Branch_Resteers ) / ##Fetch_Latency + MS ),,,,#Assist * ( Fetch_Latency * ( MS_Switches + Branch_Resteers * ( Clears_Resteers + #Umisp * Mispredicts_Resteers ) / ##Branch_Resteers ) / ##Fetch_Latency + MS ),,,,,#Assist * Fetch_Latency * ( MS_Switches + Branch_Resteers * ( Clears_Resteers + Mispredicts_Resteers * #Umisp ) / ##Branch_Resteers ) / ##Fetch_Latency,,,,,,,,,,Slots,,,5.1,MS,,pub/v4.6,0,;bot;,,,,
Aux,#Assist_Retired,,,,,,,,,,,,,,,,,,,,,,#Assist * Heavy_Operations,,,,,,,,,,Slots,,,4.6,MS,,pub/5.0,0,;bot;,,,,
Aux,#Core_Bound_Cycles,,,,,,,EXE_ACTIVITY.EXE_BOUND_0_PORTS + #Few_Uops_Executed_Threshold,,,,,,,,,,,,,,,Ports_Utilized_0 * CLKS + #Few_Uops_Executed_Threshold,,,,,,,,,,Count,,,4.7,PortsUtil,,pub/v4,3,;bot;,,,,
Aux,#Cycles_0_Ports_Utilized,,,,,,,,,,,,,,,,,#NA,,,,,UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY,,( UOPS_EXECUTED.CORE:i1:c1 ) / 2 if #SMT_on else ( CYCLE_ACTIVITY.STALLS_TOTAL - #Frontend_RS_Empty_Cycles ),,,,( UOPS_EXECUTED.CORE:i1:c1 ) / 2 if #SMT_on else ( #STALLS_TOTAL - #Frontend_RS_Empty_Cycles ),,,,Count,,,4.2,,,pub/v4.6,4,;bot;,,,,
Aux,#Cycles_1_Port_Utilized,,,,,,,,,,,,,,,,,#NA,,,,,( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL,,( UOPS_EXECUTED.CORE:c1 - UOPS_EXECUTED.CORE:c2 ) / 2 if #SMT_on else ( UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ),,( UOPS_EXECUTED.CORE:c1 - UOPS_EXECUTED.CORE:c2 ) / 2 if #SMT_on else ( UOPS_EXECUTED.CORE:c1 - UOPS_EXECUTED.CORE:c2 ),,( UOPS_EXECUTED.CORE:c1 - UOPS_EXECUTED.CORE:c2 ) / 2 if #SMT_on else ( UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ),,,,Count,,,3.5,,,pub/5.0,4,;bot;,,,,
Aux,#Cycles_2_Ports_Utilized,,,,,,,,,,,,,,,,,#NA,,,,,( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL,,( UOPS_EXECUTED.CORE:c2 - UOPS_EXECUTED.CORE:c3 ) / 2 if #SMT_on else ( UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC ),,( UOPS_EXECUTED.CORE:c2 - UOPS_EXECUTED.CORE:c3 ) / 2 if #SMT_on else ( UOPS_EXECUTED.CORE:c2 - UOPS_EXECUTED.CORE:c3 ),,( UOPS_EXECUTED.CORE:c2 - UOPS_EXECUTED.CORE:c3 ) / 2 if #SMT_on else ( UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC ),,,,Count,,,3.5,,,pub/5.0,4,;bot;,,,,
Aux,#Cycles_3m_Ports_Utilized,,,,,,,,,,,,,,,,,#NA,,,,,UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3,,( UOPS_EXECUTED.CORE:c3 / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC,,( UOPS_EXECUTED.CORE:c3 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE:c3,,( UOPS_EXECUTED.CORE:c3 / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC,,#NA,,Count,,,3.5,,,pub/5.0,4,;bot;,,,,
Aux,#DurationTimeInSeconds,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,DurationTimeInMilliSeconds / 1000,,Count,,,4.1,,,pub/v3,i,;bot;EDP;perf;VTune,,,,
Aux,#Exe_Ports,,,,,,,18,,,,,,12,,,,10,,,,,,,,,8,,,,6,,Constant,,,4.4,,,pub/v4.4,,,,,,
Aux,#Execute_Cycles,,,,,,,#NA,,,,,,,,,,,,,,,( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.THREAD:c1,,( UOPS_EXECUTED.CORE:c1 / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC,,( UOPS_EXECUTED.CORE:c1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE:c1,,( UOPS_EXECUTED.CORE:c1 / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC,,( UOPS_DISPATCHED.CORE:c1 / 2 ) if #SMT_on else UOPS_DISPATCHED.CORE:c1,,Count,,,2.9,,,pub,i,;,,,,
Aux,#FB_Factor,,,,,,,,,,,,,,,,,,,,,,1 + #FBHit_per_L1Miss / 2,,,,,,,,#NA,,Metric,factor used for metrics associating fixed costs for FB Hits - according to probability theory if all FB Hits come at a random rate in original L1_Miss cost interval then the average cost for each one is 0.5 of the fixed cost,,4.1,,,pub/5.0,i,;bot;,,,,
Aux,#FBHit_per_L1Miss,,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS,,,,,,,,#NA,,Metric,,,4.5,,,pub,i,;bot;,,,,
Aux,#Fetched_Uops,,,,,,,,,,,,,,,,,,,IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS,IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS,,IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS,,,,,,,,( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) ,,Count,,,4.5,,,pub,i,;,,,,
Aux,#Few_Uops_Executed_Threshold,,,,,,,,,,,,,EXE_ACTIVITY.1_PORTS_UTIL + Retiring * EXE_ACTIVITY.2_3_PORTS_UTIL,,,,,,,,,EXE_ACTIVITY.1_PORTS_UTIL + Retiring * EXE_ACTIVITY.2_PORTS_UTIL,,UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( IPC > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC,,UOPS_EXECUTED.CORE:c3 if ( IPC > 1.8 ) else UOPS_EXECUTED.CORE:c2,,UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( IPC > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC,,UOPS_DISPATCHED.THREAD:c3 if ( IPC > 1.8 ) else UOPS_DISPATCHED.THREAD:c2,,Count,,,4.9,PortsUtil,,pub,2,;bot;,,,,
Aux,#FLOP_Count,,,,,,,FP_ARITH_OPS_RETIRED.SCALAR + 2 * FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_OPS_RETIRED.4_FLOPS + 8 * FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE,( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ),,,,( 1 * ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF ) + 2 * ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF ) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * ( FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS ) + 16 * ( FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF ) if #FP16 else ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ),FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE,,,,FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE,,,,FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE,,,FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE,,#NA,,,,( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ),,Count,Floating Point computational (arithmetic) Operations Count,,4.8,Flops;HPC,,pub,i,;,,,,
Aux,#FP_Arith_Scalar,,,,,,,FP_ARITH_OPS_RETIRED.SCALAR,,,,,FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR if #FP16 else FP_ARITH_INST_RETIRED.SCALAR,,,,,,,,,,,,FP_ARITH_INST_RETIRED.SCALAR,,#NA,,,,FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE,,Count,,,4.8,Flops;HPC,,pub,i,;,,,,
Aux,#FP_Arith_Vector,,,,,,,FP_ARITH_OPS_RETIRED.VECTOR,,,,,FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.VECTOR if #FP16 else FP_ARITH_INST_RETIRED.VECTOR,,,,,FP_ARITH_INST_RETIRED.VECTOR,FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16:u0xe0,,,FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc,,,FP_ARITH_INST_RETIRED.VECTOR,,#NA,,,,FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE,,Count,,,4.8,Flops;HPC,,pub,i,;,,,,
Aux,#Frontend_RS_Empty_Cycles,,,,,,,,,,,,,,,,,,,,,,#NA,,,,,,,,RS_EVENTS.EMPTY_CYCLES if ( Fetch_Latency > 0.1 ) else 0,,Count,,,3.1,,,pub,2,;,,,,
Aux,#Frontend_Latency_Cycles,,,,,,,,,,,,,,,,,,,,,,,,#NA,,,,,,"min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE )",,Count,,,3,,,pub,2,;,,,,
Aux,#HighIPC,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,IPC / #Pipeline_Width,,Metric,,> 0.35,3.5,,,pub,2,;,,,,
Aux,#ITLB_Miss_Cycles,,,,,,,,,,,,,,,,,,,,,,#NA,,( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION:c1 + 7 * ITLB_MISSES.WALK_COMPLETED ),,( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ),,,,( 12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ),,Count,,,4.1,MemoryTLB,,pub,3,;,,,,
Aux,#L2_Bound_Ratio,,,,,,,,,,,,,#NA,,,,,,,,,( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CLKS,,,,,,,,#NA,,Fraction,,,3.1,,,pub,3,;bot;,,,,
Aux,#Light_Ops_Sum,,,,,,,Retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + ( #FP_Arith_Scalar + #FP_Arith_Vector ) / #Retired_Slots  +  ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128  +  INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / #Retired_Slots  + Memory_Operations + Fused_Instructions + Non_Fused_Branches,,,,,,FP_Arith + Int_Operations + Memory_Operations + Fused_Instructions + Non_Fused_Branches,,,,FP_Arith + Memory_Operations + Branch_Instructions,,,,,FP_Arith + Memory_Operations + Fused_Instructions + Non_Fused_Branches ,,,,,,,,,,Count,,,4.7,,,pub/v4.3,L3,,,,,
Aux,#LOAD_L1_MISS,,,,,,,,,,,,,,,,,,,,,,#NA,,,,MEM_LOAD_UOPS_RETIRED.L2_HIT_PS + MEM_LOAD_UOPS_RETIRED.L3_HIT_PS + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS,,MEM_LOAD_UOPS_RETIRED.L2_HIT_PS + MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS,,#NA,,Count,,,4.1,,,pub,i,;bot;,,,,
Aux,#LOAD_L1_MISS_NET,,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_RETIRED.L1_MISS,,,#LOAD_L1_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS,#LOAD_L1_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS_PS,#LOAD_L1_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM_PS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM_PS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM_PS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD_PS,#LOAD_L1_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS,,#NA,,Count,,,4,,,pub,i,;bot;,,,,
Aux,#LOAD_L2_HIT,,,,,,,,,#NA,,,,#NA,,,,,,,,,MEM_LOAD_RETIRED.L2_HIT_PS * ( 1 + #FBHit_per_L1Miss ),,,,,,,,#NA,,Count,,,4.3,,,pub/v4.2,i,;bot;,,,,
Aux,#LOAD_L3_HIT,,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_RETIRED.L3_HIT * #FB_Factor,,,,MEM_LOAD_UOPS_RETIRED.L3_HIT_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,#NA,,Count,,,4.1,,,pub/5.0,i,;bot;,,,,
Aux,#LOAD_LCL_MEM,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + #FBHit_per_L1Miss ),,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,#NA,,Count,,,3.4,Server,,pub,i,;bot;,,,,
Aux,#LOAD_LCL_PMM,,,,,,,,MEM_LOAD_RETIRED.LOCAL_CXL_MEM * ( 1 + #FBHit_per_L1Miss ) if #PMM_App_Direct else #NA,,#NA,#NA,,,,,,,,MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + #FBHit_per_L1Miss ) if #PMM_App_Direct else #NA,,,,,,,,,,,#NA,,Count,,,5.02,Server,,pub,i,;bot;,,,,
Aux,#LOAD_RMT_FWD,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + #FBHit_per_L1Miss ) if #DS else 0,,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,#NA,,Count,,,3.1,Server,,pub,i,;bot;,,,,
Aux,#LOAD_RMT_HITM,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + #FBHit_per_L1Miss ) if #DS else 0,,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,#NA,,Count,,,3.1,Server,,pub,i,;bot;,,,,
Aux,#LOAD_RMT_MEM,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + #FBHit_per_L1Miss ) if #DS else 0,,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,#NA,,Count,,,3.1,Server,,pub,i,;bot;,,,,
Aux,#LOAD_RMT_PMM,,,,,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_CXL_MEM * ( 1 + #FBHit_per_L1Miss ) if #PMM_App_Direct else #NA,,#NA,#NA,,,,,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + #FBHit_per_L1Miss ) if #PMM_App_Direct else #NA,,,,,,,,,,,#NA,,Count,,,5.02,Server,,pub,i,;bot;,,,,
Aux,#LOAD_XSNP_HIT,,,,,,,MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD,,,,,,,MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - #True_XSNP_HitM_Fraction ),,,,,,,MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS * ( 1 - #True_XSNP_HitM_Fraction ),MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS,,,,MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,#NA,,Count,,,4.7,Offcore;Snoop,,pub/5.0,i,;bot;,,,,
Aux,#LOAD_XSNP_HITM,,,,,,,MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM,,,,,,,MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * #True_XSNP_HitM_Fraction,,,,,,,MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS * #True_XSNP_HitM_Fraction,MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS,,,,MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,#NA,,Count,,,4.7,Offcore;Snoop,,pub/5.0,i,;bot;,,,,
Aux,#LOAD_XSNP_MISS,,,,,,,,,,,,,,,,,,,,,,MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS,,,,MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,#NA,,Count,,,4.7,Snoop,,pub/5.0,i,;bot;,,,,
Aux,#MEM_Bound_Ratio,,,,,,,MEMORY_STALLS.MEM / CLKS,,,,,,MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS,,,,,,,,,CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + #L2_Bound_Ratio - L2_Bound,,,,,,,,,,Fraction,,,4.1,,,pub,3,;bot;,,,,
Aux,#Mem_DDR_Hit_Fraction,,,,,,,,( 19 * #LOAD_RMT_MEM + 10 * ( #LOAD_LCL_MEM + #LOAD_RMT_FWD + #LOAD_RMT_HITM ) ) / ( ( 19 * #LOAD_RMT_MEM + 10 * ( #LOAD_LCL_MEM + #LOAD_RMT_FWD + #LOAD_RMT_HITM ) ) + ( 25 * #LOAD_LCL_PMM + 33 * #LOAD_RMT_PMM ) ) if #PMM_App_Direct else 1,,#NA,#NA,,,,,,,,( 19 * #LOAD_RMT_MEM + 10 * ( #LOAD_LCL_MEM + #LOAD_RMT_FWD + #LOAD_RMT_HITM ) ) / ( ( 19 * #LOAD_RMT_MEM + 10 * ( #LOAD_LCL_MEM + #LOAD_RMT_FWD + #LOAD_RMT_HITM ) ) + ( 25 * #LOAD_LCL_PMM + 33 * #LOAD_RMT_PMM ) ) if #PMM_App_Direct else 1,,,,,,,,,,,#NA,,Fraction,,,5.02,Server,,pub,3,;bot;,,,,
Aux,#Mem_L2_Store_Cost,,,,,,,,,,,,,,,,,10,,,,11,,,,,,,9,,,,Constant,,,4,,,pub/5.0,4,;bot;,,,,
Aux,#Mem_L3_Hit_Fraction,,,,,,,,,,,,,,,,,,,,,,#NA,,,,MEM_LOAD_UOPS_RETIRED.L3_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.L3_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.L3_MISS_PS ),,MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS ),MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS ),MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS ),,Fraction,,,3,,,pub,3,;,,,,
Aux,#Mem_Lock_St_Fraction,,,,,,,,,,,,,,,,,,,,,,MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES,,,,,,MEM_UOPS_RETIRED.LOCK_LOADS_PS / MEM_UOPS_RETIRED.ALL_STORES_PS,,,,Fraction,,,3,,,pub/5.0,4,;bot;,,,,
Aux,#Memory_Bound_Fraction,,,,,,,,,,,,,#NA,,,,,,,,,( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / #Backend_Bound_Cycles,,( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / #Backend_Bound_Cycles,,,,,,( #STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / #Backend_Bound_Cycles,,Fraction,,,4,,,pub,2,;bot;,,,,
Aux,#Mispred_Clears_Fraction,,,,,,,,,,,,,Branch_Mispredicts / Bad_Speculation,,,,,,,,,,,,,,,,,BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ),,Fraction,,,4.4,BrMispredicts,,pub,2,;bot;,,,,
Aux,#OCR_all_rfo_l3_hit_snoop_hitm,,,,,,,,,,,,,,,,,#NA,,OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE,,OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE,OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM,,,,,,,,,,Count,,,4,Offcore,,pub/5.0,i,;bot;,,,,
Aux,#OCR_all_rfo_l3_miss_remote_hitm,,,,,,,,,,,,,,,,,#NA,,OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM,,OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM,,,,,,,,,,,Count,,,4,Offcore;Server,,pub/5.0,i,;bot;,,,,
Aux,#ORO_Demand_RFO_C1,,,,,,,,,,,,,,,,,,,,,,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO )",,,,Count,,,2.9,Offcore,,pub/5.0,4,;bot;,,,,
Aux,#ORO_DRD_Any_Cycles,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD )",,Count,,,3.1,Offcore,,pub,4,;bot;,,,,
Aux,#ORO_DRD_BW_Cycles,,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c12 )","min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4 )",,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c12 )",,,,,,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4 )",,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c6 )",,Count,,,3.1,Offcore,,pub,4,;bot;,,,,
Aux,#SQ_Full_Cycles,,,,,,,,,,,,,,,,,#NA,,,,,,,,,,,( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL,,,,Count,,,4,Offcore,,pub/5.0,4,;bot;,,,,
Aux,#STALLS_MEM_ANY,,,,,,,,,,,,,,,,,,,,,,,,#NA,,,,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING )",,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_L1D_PENDING )",,Count,,,3.1,,,pub,2,;,,,,
Aux,#STALLS_TOTAL,,,,,,,,,,,,,,,,,,,,,,,,#NA,,,,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE )",,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_DISPATCH )",,Count,,,2.9,,,pub,2,;,,,,
Aux,#Store_L2_Hit_Cycles,,,,,,,,,,,,,MEM_STORE_RETIRED.L2_HIT * #Mem_L2_Store_Cost * ( 1 - #Mem_Lock_St_Fraction ),,,,,,,,,,,,,,,L2_RQSTS.RFO_HIT * #Mem_L2_Store_Cost * ( 1 - #Mem_Lock_St_Fraction ),,#NA,,Count,,,3.1,,,pub/5.0,4,;bot;,,,,
Aux,#True_XSNP_HitM_Fraction,,,,,,,#NA,,,,,,,OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ),,OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ),,,OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ),,OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ),,,,,,,,,#NA,,Fraction,,,3.5,Offcore;Snoop,,pub/5.0,3,;bot;,,,,
Aux,#Mem_L3_Weight,,,,,,,,,,,,,,,,,,,,,,#NA,,,,,,,,7,,Constant,,,2.5,,,pub,-,;,,,,
Aux,#Mem_STLB_Hit_Cost,,,,,,,,,,,,,,,,,7,,,,,9,,,,8,,,,7,,Constant,,,4.2,MemoryTLB,,pub,4,;bot;,,,,
Aux,#Mem_XSNP_HitM_Cost,,,,,,,,,,,,81 * Core_Frequency,28 * Core_Frequency,54 * Core_Frequency,,48 * Core_Frequency,32.5 * Core_Frequency,,,,47.5 * Core_Frequency,22 * Core_Frequency,,,,,,60,,,,NanoSeconds,L3 issuing the snoop,,4.8,Snoop,,pub/5.0,4,;bot;,,,,
Aux,#Mem_XSNP_Hit_Cost,,,,,,,,,,,,79 * Core_Frequency,27 * Core_Frequency,53 * Core_Frequency,,47.5 * Core_Frequency,27 * Core_Frequency,,,,47.5 * Core_Frequency,20 * Core_Frequency,,,,,,43,,,,NanoSeconds,L3 issuing the snoop,,4.8,Snoop,,pub/5.0,4,;bot;,,,,
Aux,#Mem_XSNP_None_Cost,,,,,,,,,,,,37 * Core_Frequency,12 * Core_Frequency,22.5 * Core_Frequency,,23 * Core_Frequency,12.5 * Core_Frequency,,,,20.5 * Core_Frequency,10 * Core_Frequency,,,,,41,29,,,,NanoSeconds,L3 not issuing a snoop,,4.7,Snoop,,pub/5.0,4,;bot;,,,,
Aux,#Mem_Local_DRAM_Cost,,,,,,,,,,,,109 * Core_Frequency,,,,66.5 * Core_Frequency,,,,,80 * Core_Frequency,,,,,,200,,,,,NanoSeconds,,,4.8,Server,,pub/5.0,5,;bot;,,,,
Aux,#Mem_Remote_DRAM_Cost,,,,,,,,,,,,190 * Core_Frequency,,,,131 * Core_Frequency,,,,,147.5 * Core_Frequency,,,,,,310,,,,,NanoSeconds,,,4.8,Server,,pub/5.0,5,;bot;,,,,
Aux,#Mem_Remote_HitM_Cost,,,,,,,,,,,,170 * Core_Frequency,,,,120 * Core_Frequency,,,,,110 * Core_Frequency,,,,,,200,,,,,NanoSeconds,,,4.8,Server,,pub/5.0,5,;bot;,,,,
Aux,#Mem_Remote_Fwd_Cost,,,,,,,,,,,,170 * Core_Frequency,,,,120 * Core_Frequency,,,,,110 * Core_Frequency,,,,,,180,,,,,NanoSeconds,,,4.8,Server,,pub/5.0,5,;bot;,,,,
Aux,#Mem_L2_Hit_Cost,,,,,,,,,,,,4.4 * Core_Frequency,3 * Core_Frequency,5 * Core_Frequency,,4 * Core_Frequency,,,,,,3.5 * Core_Frequency,,,,,180,,,,,NanoSeconds,,,4.8,,,pub/5.0,5,;bot;,,,,
Aux,#BAClear_Cost,,,,,,,,,,,,,#NA,,,,10,,,,,9,,,,,,,,12,,Constant,,,4.4,,,pub,i,;bot;,,,,
Aux,#MS_Switches_Cost,,,,,,,,,,,,,,,,,3,,,,,,,,,2,,,,3,,Constant,,,4,,,pub,3,;bot;,,,,
Aux,#Avg_Assist_Cost,,,,,,,,,,,,,( 99 *3 + 63 + 30 ) / 5,,,,,,,,,34,,,,,,66,,,,Constant,,,4.6,,,pub/v4.6,3,;bot;,,,,
Aux,#UC_Scale_Factor,,,,,,,1,,,,,,,,,,,,,,,,,,,,,,,#NA,,Constant,,,5,,,,,,,,,
Aux,#PERF_METRICS_SUM,,,,,,,,,,,,,,,,,PERF_METRICS.FRONTEND_BOUND + PERF_METRICS.BAD_SPECULATION + PERF_METRICS.RETIRING + PERF_METRICS.BACKEND_BOUND,,,,,,,,,,,,,#NA,,Count,,,4.1,TmaL1,,pub/v4,1,;bot;perf,,,,
Aux,#Pipeline_Width,,,,,,,8,,,,,,6,,,,5,,,,,,,,,,,,,4,,Constant,,,4.1,TmaL1,,pub,1,;bot;perf,,,,
Aux,#DSB_Width,,,,,,,12,,,,,,8,,,,,,,,,6,,,,,,,,4,,Constant,,,5.02,,,,,ptools,,,,
Aux,#MITE_Width,,,,,,,8,,,,,,6,,,,,,,,,5,,,,,,,,,,Constant,,,5.02,,,,,ptools,,,,
Aux,#Decode_Width,,,,,,,8,,,,,,6,,,,,,,,,4,,,,,,,,,,Constant,,,5.02,,,,,ptools,,,,
Aux,#MS_Width,,,,,,,,,,,,,,,,,,,,,,4,,,,,,,,,,Constant,,,5.02,,,,,ptools,,,,
Aux,#Retire_Width,,,,,,,12,,,,,,,,,,8,,,,,4,,,,,,,,,,Constant,,,5.02,,,,,ptools,,,,
Aux,#Recovery_Cycles,,,,,,,,,,,,,#NA,,,,#NA,,,,,,,,,,,,,( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES,,Count,,,4.2,,,pub,1,;bot;,,,,
Aux,#Retire_Fraction,,,,,,,,,,,,,,,,,UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY,,,,,,,,,,,,,#Retired_Slots / UOPS_ISSUED.ANY,,Fraction,,,4.6,BrMispredicts,,pub,2,;bot;,,,,
Aux,#Retired_Slots,,,,,,,,,,,,,,,,,Retiring * SLOTS,,,,,,,,,,,,,UOPS_RETIRED.RETIRE_SLOTS,,Count,,,4.1,TmaL1,,pub,1,;bot;perf,,,,
Aux,#OneMillion,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,1000000,,Constant,,,2.6,,,pub,i,;bot;,,,,
Aux,#OneBillion,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,1000000000,,Constant,,,3,,,pub,i,;bot;,,,,
Aux,#Energy_Unit,,,,,,,,,,,,,,,,,,,,,,,,,,61,,15.6,,,,Constant,,,3,,,pub,i,;,,,,
Aux,#Errata_Whitelist,,,,,,,,,#NA,,,SPR121;SPR103,ADL038;ADL066,,,,#NA,,,,,SKL091,,BDE69;BDE70,,,,,,,,Constant,,,4.8,,,pub,i,;toplev,,,,
Aux,#SMT_on,,,,,,,#NA,,,,,,,,,,,,,,,,,,,,,,,1,,SystemParameter,whether Simultaneous Multi Threading (SMT) is enabled (in BIOS),,2.7,SMT;Summary,,pub/v3,1,;bot;,EDP ? system.sockets[0][0].size > 1 : perf ? /sys/devices/system/cpu/smt/control : Intel-way-SMT-on,,,
Aux,#EBS_Mode,,,,,,,,,,,,,,,,,#NA,,,,,,,,,,,,,0,,ExternalParameter,Use ratios that apply to Event Based Sampling where applicable. By setting this flag user acks homogeneous behavior across all processors. Note this may increase counter multiplexing.,,4.6,,,pub/v3.3,1,;bot;vtune,,,,
Aux,Num_CPUs,,,,,,,NUM_CORES if NUM_CORES else 16,NUM_CORES * NUM_SOCKETS * NUM_THREADS if NUM_CORES else 320 / ( 2 - #SMT_on ),,,,NUM_CORES * NUM_SOCKETS * NUM_THREADS if NUM_CORES else 224 / ( 2 - #SMT_on ),NUM_CORES * NUM_THREADS if NUM_CORES else ( 8 + 16 / ( 2 - #SMT_on ) ),NUM_CORES * NUM_THREADS if NUM_CORES else 16 / ( 2 - #SMT_on ),,NUM_CORES * NUM_SOCKETS * NUM_THREADS if NUM_CORES else 160 / ( 2 - #SMT_on ),,,112 if #SMT_on else 56,,,,,,,,,,,8 if #SMT_on else 4,,SystemParameter,Number of logical processors (enabled or online) on the target system,,4.6,Summary,,pub/v4.6,,;,EDP ? system.sockets[0].cpus.count : perf ? Linux-way-Num-CPUs  : Intel-way-Num-CPUs,,,
Aux,#Memory,,,,,,,,,,0,2,0,,,,,,,1,,,,,,,,,,,#NA,,ExternalParameter,,,4.8,Server,,pub/v3.5,3,;bot;,,,,
Aux,#PMM_App_Direct,,,,,,,,,,,,,,,,,,,1 if #Memory == 1 else 0,,,,,,,,,,,#NA,,ExternalParameter,,,4.5,Server,,pub,3,;bot;,,,,
Aux,#HBM,,,,,,,,0,,,,1 if #Memory > 1 else 0,,,,,,,,,,,,,,,,,,,,ExternalParameter,,,4.7,Server,,pub/v4.6,,;bot;,,,,
Aux,DurationTimeInMilliSeconds,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,SystemParameter,The duration time in milli-seconds of the profile,,4.2,Summary,,pub,,;bot;EDP;perf;VTune,EDP ? 1000 : duration-time,,,
Aux,Dependent_Loads_Weight,,,,,,,#NA,,,,,,,,,,,,,,,20,,,,,,,,,,SystemParameter,A system parameter for dependent-loads (pointer chasing like access pattern) of the workload. An integer fraction in range from 0 (no dependent loads) to 100 (all loads are dependent loads),,4.8,MemoryLat,,pub/5.0,,;bot;,,,,
Aux,#PERF_METRICS_MSR,,,,,,,,,,,,,,,,,1,,,,,,,,,,,,,#NA,,ExternalParameter,,,4.2,,,,1,;bot;toplev;vtune,,,,
Aux,#FP16,,,,,,,,,,,,1,,,,,,,,,,,,,,,,,,,,ExternalParameter,A system parameter to indicate FP16 on vector stack and AMX (any data type) are enabled,,4.6,Flops,,pub/v4.5,,,,,,
Aux,#DS,,,,,,,,,,,,,,,,,,,,,,,,,,,,,1,0,,ExternalParameter,A system parameter to indicate Dual-Socket is enabled,,4.8,Server,,pub/5.0,,;bot;,,,,