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mkorbel1mkorbel1
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Fix nested array naming in typed structure port synthesis (#698)
1 parent a4ca8b3 commit eb381bb

2 files changed

Lines changed: 227 additions & 3 deletions

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‎lib/src/synthesizers/utilities/synth_module_definition.dart‎

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -320,6 +320,23 @@ class SynthModuleDefinition {
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/// definition.
321321
final List<Module> supportingModules = [];
322322

323+
/// Retains [signal] and every array ancestor needed to name and declare it.
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void _retainInternalSignal(SynthLogic signal) {
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final signalAndAncestors = <SynthLogic>[signal];
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while (signal is SynthLogicArrayElement) {
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signal = signal.parentArray.resolved;
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signalAndAncestors.add(signal);
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}
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for (final retainedSignal in signalAndAncestors.reversed) {
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if (!inputs.contains(retainedSignal) &&
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!outputs.contains(retainedSignal) &&
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!inOuts.contains(retainedSignal)) {
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internalSignals.add(retainedSignal);
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}
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}
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}
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323340
/// Takes all the leaf elements of [port] and drives [port] with them, each
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/// with a partial assignment.
325342
///
@@ -334,7 +351,7 @@ class SynthModuleDefinition {
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var idx = 0;
335352
for (final leafElement in port.leafElements) {
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final leafSynth = getSynthLogic(leafElement)!;
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internalSignals.add(leafSynth);
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_retainInternalSignal(leafSynth);
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assignments.add(
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PartialSynthAssignment(
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leafSynth,
@@ -358,7 +375,7 @@ class SynthModuleDefinition {
358375
var idx = 0;
359376
for (final leafElement in port.leafElements) {
360377
final leafSynth = getSynthLogic(leafElement)!;
361-
internalSignals.add(leafSynth);
378+
_retainInternalSignal(leafSynth);
362379

363380
// this is DISCONNECTED, just a module used for synthesizing
364381
final subsetMod = _BusSubsetForStructSlice(
@@ -541,7 +558,7 @@ class SynthModuleDefinition {
541558
!inOuts.contains(synthReceiver),
542559
'Internal signals should not be ports also.',
543560
);
544-
internalSignals.add(synthReceiver);
561+
_retainInternalSignal(synthReceiver);
545562
}
546563

547564
final receiverIsSubmoduleInOut =

‎test/nested_array_struct_port_synthesis_test.dart‎

Lines changed: 207 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,207 @@
1+
// Copyright (C) 2026 Intel Corporation
2+
// SPDX-License-Identifier: BSD-3-Clause
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//
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// nested_array_struct_port_synthesis_test.dart
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// Tests synthesis of nested LogicArray fields in typed LogicStructure ports.
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//
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// 2026 August 18
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// Author: Max Korbel <max.korbel@intel.com>
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import 'package:rohd/rohd.dart';
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import 'package:rohd/src/utilities/simcompare.dart';
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import 'package:test/test.dart';
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class ArrayRecord extends LogicStructure {
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final Logic header;
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final LogicArray entries;
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final Logic trailer;
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factory ArrayRecord({
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String name = 'arrayRecord',
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List<int> dimensions = const [3],
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int numUnpackedDimensions = 0,
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}) =>
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ArrayRecord._(
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Logic(name: 'header', width: 2),
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LogicArray(
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dimensions,
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4,
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name: 'entries',
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numUnpackedDimensions: numUnpackedDimensions,
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),
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Logic(name: 'trailer', width: 3),
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name: name,
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);
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ArrayRecord._(
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this.header,
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this.entries,
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this.trailer, {
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required String name,
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}) : super([header, entries, trailer], name: name);
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@override
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ArrayRecord clone({String? name}) => ArrayRecord(
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name: name ?? this.name,
46+
dimensions: entries.dimensions,
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numUnpackedDimensions: entries.numUnpackedDimensions,
48+
);
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}
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51+
class ArrayRecordProducer extends Module {
52+
late final ArrayRecord outputData;
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54+
ArrayRecordProducer({
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required List<int> dimensions,
56+
required int numUnpackedDimensions,
57+
}) {
58+
outputData = addTypedOutput(
59+
'outputData',
60+
({name = 'outputData'}) => ArrayRecord(
61+
name: name,
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dimensions: dimensions,
63+
numUnpackedDimensions: numUnpackedDimensions,
64+
),
65+
);
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67+
outputData.header <= Const(0, width: outputData.header.width);
68+
for (final entry in outputData.entries.leafElements) {
69+
entry <= Const(0, width: entry.width);
70+
}
71+
outputData.trailer <= Const(0, width: outputData.trailer.width);
72+
}
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}
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75+
class ArrayRecordConsumer extends Module {
76+
late final Logic observed;
77+
78+
ArrayRecordConsumer(ArrayRecord source, {required bool consumeInput}) {
79+
final inputData = addTypedInput('inputData', source);
80+
81+
observed = addOutput('observed')
82+
..gets(
83+
consumeInput ? inputData.entries.leafElements.first[0] : Const(0),
84+
);
85+
}
86+
}
87+
88+
class ArrayRecordHierarchy extends Module {
89+
ArrayRecordHierarchy({
90+
List<int> dimensions = const [3],
91+
int numUnpackedDimensions = 0,
92+
bool consumeInput = false,
93+
bool connectProducerDirectly = false,
94+
}) {
95+
final producer = ArrayRecordProducer(
96+
dimensions: dimensions,
97+
numUnpackedDimensions: numUnpackedDimensions,
98+
);
99+
final source = connectProducerDirectly
100+
? producer.outputData
101+
: ArrayRecord(
102+
name: 'intermediate',
103+
dimensions: dimensions,
104+
numUnpackedDimensions: numUnpackedDimensions,
105+
);
106+
final consumer = ArrayRecordConsumer(
107+
source,
108+
consumeInput: consumeInput,
109+
);
110+
111+
if (!connectProducerDirectly) {
112+
source.gets(producer.outputData);
113+
}
114+
addOutput('observed').gets(consumer.observed);
115+
}
116+
}
117+
118+
class RootArrayPassThrough extends Module {
119+
late final LogicArray outputData;
120+
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RootArrayPassThrough(LogicArray source) {
122+
final inputData = addTypedInput('inputData', source);
123+
outputData = addTypedOutput('outputData', inputData.clone)..gets(inputData);
124+
}
125+
}
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127+
void main() {
128+
tearDown(Simulator.reset);
129+
130+
group('nested array structure input synthesis', () {
131+
final testCases = [
132+
(
133+
name: 'unused one-dimensional packed array',
134+
dimensions: const [3],
135+
numUnpackedDimensions: 0,
136+
consumeInput: false,
137+
connectProducerDirectly: false,
138+
expectedDeclaration: 'logic [2:0][3:0] inputData_entries;',
139+
),
140+
(
141+
name: 'unused multi-dimensional packed array',
142+
dimensions: const [2, 3],
143+
numUnpackedDimensions: 0,
144+
consumeInput: false,
145+
connectProducerDirectly: false,
146+
expectedDeclaration: 'logic [1:0][2:0][3:0] inputData_entries;',
147+
),
148+
(
149+
name: 'unused array with an unpacked dimension',
150+
dimensions: const [2, 3],
151+
numUnpackedDimensions: 1,
152+
consumeInput: false,
153+
connectProducerDirectly: false,
154+
expectedDeclaration: 'logic [2:0][3:0] inputData_entries [1:0];',
155+
),
156+
(
157+
name: 'internally consumed nested array input',
158+
dimensions: const [3],
159+
numUnpackedDimensions: 0,
160+
consumeInput: true,
161+
connectProducerDirectly: false,
162+
expectedDeclaration: null,
163+
),
164+
(
165+
name: 'producer output connected directly',
166+
dimensions: const [3],
167+
numUnpackedDimensions: 0,
168+
consumeInput: false,
169+
connectProducerDirectly: true,
170+
expectedDeclaration: null,
171+
),
172+
];
173+
174+
for (final testCase in testCases) {
175+
test(testCase.name, () async {
176+
final module = ArrayRecordHierarchy(
177+
dimensions: testCase.dimensions,
178+
numUnpackedDimensions: testCase.numUnpackedDimensions,
179+
consumeInput: testCase.consumeInput,
180+
connectProducerDirectly: testCase.connectProducerDirectly,
181+
);
182+
await module.build();
183+
184+
final generated = module.generateSynth();
185+
186+
expect(generated, contains('module ArrayRecordHierarchy'));
187+
expect(generated, contains('.inputData('));
188+
if (testCase.expectedDeclaration case final expectedDeclaration?) {
189+
expect(generated, contains(expectedDeclaration));
190+
}
191+
SimCompare.checkIverilogVector(module, [], buildOnly: true);
192+
});
193+
}
194+
});
195+
196+
test('root typed LogicArray ports retain their declaration shape', () async {
197+
final module = RootArrayPassThrough(LogicArray([2, 3], 4));
198+
await module.build();
199+
200+
final generated = module.generateSynth();
201+
202+
expect(generated, contains('input logic [1:0][2:0][3:0] inputData'));
203+
expect(generated, contains('output logic [1:0][2:0][3:0] outputData'));
204+
expect(generated, contains('assign outputData = inputData;'));
205+
SimCompare.checkIverilogVector(module, [], buildOnly: true);
206+
});
207+
}

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