-
Notifications
You must be signed in to change notification settings - Fork 4
Expand file tree
/
Copy path1966-Define-double-floating-point-instructions-for-S.patch
More file actions
490 lines (423 loc) · 20.1 KB
/
Copy path1966-Define-double-floating-point-instructions-for-S.patch
File metadata and controls
490 lines (423 loc) · 20.1 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Steven Goldade <smgoldade@gmail.com>
Date: Tue, 9 Jun 2020 11:00:58 -0500
Subject: [PATCH] 1966: Define double floating point instructions for SuperH
Fix FSUB instructions
Add floating point context registers
Update FSCHG to use a simple global context change
---
.../SuperH/data/languages/superh.pspec | 6 +
.../SuperH/data/languages/superh.sinc | 223 +++++++++++++-----
2 files changed, 164 insertions(+), 65 deletions(-)
diff --git a/Ghidra/Processors/SuperH/data/languages/superh.pspec b/Ghidra/Processors/SuperH/data/languages/superh.pspec
index 114b5c47a8..7b583e7b7d 100644
--- a/Ghidra/Processors/SuperH/data/languages/superh.pspec
+++ b/Ghidra/Processors/SuperH/data/languages/superh.pspec
@@ -2,4 +2,10 @@
<processor_spec>
<programcounter register="pc"/>
+ <context_data>
+ <context_set space="register">
+ <set name="fpscr_pr" val="0" description="Default floating-point precision"/>
+ <set name="fpscr_sz" val="0" description="Default floating-point size"/>
+ </context_set>
+ </context_data>
</processor_spec>
diff --git a/Ghidra/Processors/SuperH/data/languages/superh.sinc b/Ghidra/Processors/SuperH/data/languages/superh.sinc
index 53c61a466d..7e4295cee3 100644
--- a/Ghidra/Processors/SuperH/data/languages/superh.sinc
+++ b/Ghidra/Processors/SuperH/data/languages/superh.sinc
@@ -38,15 +38,16 @@ define register offset=0x200 size=8 [ dr0 dr2 dr4
# Floating-Point System Registers
define register offset=0x300 size=4 [fpscr fpul];
-# FPSCR Flags (initial value = H'0004 0001)
-@define FP_RM "fpscr[0,2]"
-@define FP_FLAG "fpscr[2,5]"
-@define FP_ENABLE "fpscr[7,5]"
-@define FP_CAUSE "fpscr[12,6]"
-@define FP_DN "fpscr[18,1]"
-@define FP_PR "fpscr[19,1]"
-@define FP_SZ "fpscr[20,1]"
-@define FP_QIS "fpscr[22,1]"
+# Floating-Point Context Registers
+define context fpscr
+ fpscr_pr= (19,19)
+ fpscr_sz= (20,20)
+;
+
+# FPSCR Flags
+@define FPSCR_PR "fpscr[19,1]"
+@define FPSCR_SZ "fpscr[20,1]"
+
@endif
@@ -148,6 +149,11 @@ define token finstr32(32)
lf_rm_20_23 = (20, 23)
lf_rn_24_27 = (24, 27)
lffrn_20_23 = (20, 23)
+
+ lfdrn_25_27 = (25, 27)
+ lfop_24_24 = (24, 24)
+ lfdrm_21_23 = (21, 23)
+ lfop_20_20 = (20, 20)
;
attach variables [ ffrn_08_11 ffrm_08_11 ffrn_04_07 ffrm_04_07 lffrm_24_27 lffrn_24_27 lffrm_20_23 lffrn_20_23 ]
@@ -156,7 +162,7 @@ attach variables [ ffrn_08_11 ffrm_08_11 ffrn_04_07 ffrm_04_07 lffrm_24_27 lffrn
attach variables [ f_rm_04_07 f_rn_08_11 lf_rm_20_23 lf_rn_24_27 ]
[r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15];
-attach variables [ fdrn_09_11 fdrm_09_11 fdrn_05_07 fdrm_05_07 ]
+attach variables [ fdrn_09_11 fdrm_09_11 fdrn_05_07 fdrm_05_07 lfdrn_25_27 lfdrm_21_23 ]
[dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14];
@endif
@@ -507,7 +513,6 @@ simm20s: "#"value is l_simm20_20_23 & l_imm20_00_15
[ value = ((l_simm20_20_23 << 16) | l_imm20_00_15) << 8; ]
{ export *[const]:4 value; }
-
# MOVI20 #imm20, Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii imm → sign extension → Rn
:movi20 simm20, l_rn_24_27
is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0000 & simm20
@@ -1987,217 +1992,301 @@ define pcodeop Sleep_Standby;
#
# FABS FRn 1111nnnn01011101 |FRn| → FRn
-:fabs ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01011101
+:fabs ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01011101 & fpscr_pr=0b0
{
ffrn_08_11 = abs(ffrn_08_11);
}
-# TODO: FABS DRn 1111nnn001011101 |DRn| → DRn
+#FABS DRn 1111nnn001011101 |DRn| → DRn
+:fabs fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_00_07=0b01011101 & fop_08_08=0b0 & fpscr_pr=0b1
+{
+ fdrn_09_11 = abs(fdrn_09_11);
+}
# FADD FRm, FRn 1111nnnnmmmm0000 FRn + FRm → FRn
-:fadd ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0000
+:fadd ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0000 & fpscr_pr=0b0
{
ffrn_08_11 = ffrn_08_11 f+ ffrm_04_07;
}
-# TODO: FADD DRm, DRn 1111nnn0mmm00000 DRn + DRm → DRn
+# FADD DRm, DRn 1111nnn0mmm00000 DRn + DRm → DRn
+:fadd fdrm_05_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fdrm_05_07 & fop_04_04 = 0b0 & fop_00_03=0b0000 & fpscr_pr=0b1
+{
+ fdrn_09_11 = fdrn_09_11 f+ fdrm_05_07;
+}
# FCMP/EQ FRm, FRn 1111nnnnmmmm0100 (FRn=FRm)? 1:0 → T
-:fcmp"/eq" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0100
+:fcmp"/eq" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0100 & fpscr_pr=0b0
{
$(T_FLAG) = (ffrn_08_11 f== ffrm_04_07);
}
-# TODO: FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn=DRm)? 1:0 → T
+# FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn=DRm)? 1:0 → T
+:fcmp"/eq" fdrm_05_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fdrm_05_07 & fop_04_04 = 0b0 & fop_00_03=0b0100 & fpscr_pr=0b1
+{
+ $(T_FLAG) = (fdrn_09_11 f== fdrm_05_07);
+}
# FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn>FRm)? 1:0 → T
-:fcmp"/gt" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0101
+:fcmp"/gt" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0101 & fpscr_pr=0b0
{
$(T_FLAG) = (ffrn_08_11 f> ffrm_04_07);
}
-# TODO: FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn>DRm)? 1:0 → T
+# FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn>DRm)? 1:0 → T
+:fcmp"/gt" fdrm_05_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fdrm_05_07 & fop_04_04 = 0b0 & fop_00_03=0b0101 & fpscr_pr=0b1
+{
+ $(T_FLAG) = (fdrn_09_11 f> fdrm_05_07);
+}
# FCNVDS DRm, FPUL 1111mmm010111101 (float) DRm → FPUL
-:fcnvds fdrm_09_11, fpul is fpul & fop_12_15=0b1111 & fdrm_09_11 & fop_08_08=0b0 & fop_00_07=0b10111101
+:fcnvds fdrm_09_11, fpul is fpul & fop_12_15=0b1111 & fdrm_09_11 & fop_08_08=0b0 & fop_00_07=0b10111101 & fpscr_pr=0b1
{
fpul = float2float(fdrm_09_11);
}
# FCNVSD FPUL, DRn 1111nnn010101101 (double) FPUL → DRn
-:fcnvsd fpul, fdrn_09_11 is fpul & fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fop_00_07=0b10101101
+:fcnvsd fpul, fdrn_09_11 is fpul & fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fop_00_07=0b10101101 & fpscr_pr=0b1
{
fdrn_09_11 = float2float(fpul);
}
# FDIV FRm, FRn 1111nnnnmmmm0011 FRn/FRm → FRn
-:fdiv ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0011
+:fdiv ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0011 & fpscr_pr=0b0
{
ffrn_08_11 = ffrn_08_11 f/ ffrm_04_07;
}
-# TODO: FDIV DRm, DRn 1111nnn0mmm00011 DRn/DRm → DRn
+# FDIV DRm, DRn 1111nnn0mmm00011 DRn/DRm → DRn
+:fdiv fdrm_05_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fdrm_05_07 & fop_04_04 = 0b0 & fop_00_03=0b0011 & fpscr_pr=0b1
+{
+ fdrn_09_11 = fdrn_09_11 f/ fdrm_05_07;
+}
# FLDI0 FRn 1111nnnn10001101 0 × 00000000 → FRn
-:fldi0 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10001101
+:fldi0 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10001101 & fpscr_pr=0b0
{
ffrn_08_11 = 0x00000000;
}
# FLDI1 FRn 1111nnnn10011101 0 × 3F800000 → FRn
-:fldi1 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10011101
+:fldi1 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10011101 & fpscr_pr=0b0
{
ffrn_08_11 = 0x3F800000;
}
# FLDS FRm, FPUL 1111mmmm00011101 FRm → FPUL
-:flds ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00011101
+:flds ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00011101 & fpscr_pr=0b0
{
fpul = ffrm_08_11;
}
# FLOAT FPUL,FRn 1111nnnn00101101 (float) FPUL → FRn
-:float fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00101101
+:float fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00101101 & fpscr_pr=0b0
{
ffrn_08_11 = int2float(fpul);
}
-# TODO: FLOAT FPUL,DRn 1111nnn000101101 (double) FPUL → DRn
+# FLOAT FPUL,DRn 1111nnn000101101 (double) FPUL → DRn
+:float fpul, fdrn_09_11 is fpul & fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fop_00_07=0b00101101 & fpscr_pr=0b1
+{
+ fdrn_09_11 = int2float(fpul);
+}
# FMAC FR0, FRm, FRn 1111nnnnmmmm1110 FR0 × FRm + FRn → FRn
-:fmac fr0, ffrm_04_07, ffrn_08_11 is fr0 & fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1110
+:fmac fr0, ffrm_04_07, ffrn_08_11 is fr0 & fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1110 & fpscr_pr=0b0
{
ffrn_08_11 = ffrn_08_11 f+ (ffrm_04_07 f* fr0);
}
# FMOV FRm, FRn 1111nnnnmmmm1100 FRm → FRn
-:fmov ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1100
+:fmov ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1100 & fpscr_sz=0b0
{
ffrn_08_11 = ffrm_04_07;
}
-# TODO: FMOV DRm, DRn 1111nnn0mmm01100 DRm → DRn
+# FMOV DRm, DRn 1111nnn0mmm01100 DRm → DRn
+:fmov fdrm_05_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fdrm_05_07 & fop_04_04 = 0b0 & fop_00_03=0b1100 & fpscr_sz=0b1
+{
+ fdrn_09_11 = fdrm_05_07;
+}
# FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110 (R0+Rm) → FRn
-:fmov.s @(r0, f_rm_04_07), ffrn_08_11 is r0 & fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b0110
+:fmov.s @(r0, f_rm_04_07), ffrn_08_11 is r0 & fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b0110 & fpscr_sz=0b0
{
ffrn_08_11 = *:4 (r0 + f_rm_04_07);
}
-# TODO: FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 (R0+Rm) → DRn
+# FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 (R0+Rm) → DRn
+:fmov.d @(r0, f_rm_04_07), fdrn_09_11 is r0 & fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & f_rm_04_07 & fop_00_03=0b0110 & fpscr_sz=0b1
+{
+ fdrn_09_11 = *:8 (r0 + f_rm_04_07);
+}
# FMOV.S @Rm+, FRn 1111nnnnmmmm1001 (Rm) → FRn, Rm+ = 4
-:fmov.s @f_rm_04_07+, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1001
+:fmov.s @f_rm_04_07+, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1001 & fpscr_sz=0b0
{
ffrn_08_11 = *:4 (f_rm_04_07);
f_rm_04_07 = f_rm_04_07 + 4;
}
-# TODO: FMOV.D @Rm+, DRn 1111nnn0mmmm1001 (Rm) → DRn, Rm+ = 8
+# FMOV.D @Rm+, DRn 1111nnn0mmmm1001 (Rm) → DRn, Rm+ = 8
+:fmov.d @f_rm_04_07+, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & f_rm_04_07 & fop_00_03=0b1001 & fpscr_sz=0b1
+{
+ fdrn_09_11 = *:8 (f_rm_04_07);
+ f_rm_04_07 = f_rm_04_07 + 8;
+}
# FMOV.S @Rm, FRn 1111nnnnmmmm1000 (Rm) → FRn
-:fmov.s @f_rm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1000
+:fmov.s @f_rm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1000 & fpscr_sz=0b0
{
ffrn_08_11 = *:4 (f_rm_04_07);
}
-# TODO: FMOV.D @Rm, DRn 1111nnn0mmmm1000 (Rm) → DRn
+# FMOV.D @Rm, DRn 1111nnn0mmmm1000 (Rm) → DRn
+:fmov.d @f_rm_04_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & f_rm_04_07 & fop_00_03=0b1000 & fpscr_sz=0b1
+{
+ fdrn_09_11 = *:8 (f_rm_04_07);
+}
# FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 0111dddddddddddd (disp×4+Rm) → FRn
:fmov.s @(disp12, lf_rm_20_23), lffrn_24_27
- is lfop_28_31=0b0011 & lffrn_24_27 & lf_rm_20_23 & lfop_12_19=0b00010111 & lfdisp_00_11
+ is lfop_28_31=0b0011 & lffrn_24_27 & lf_rm_20_23 & lfop_12_19=0b00010111 & lfdisp_00_11 & fpscr_sz=0b0
[ disp12 = lfdisp_00_11 * 4; ]
{
lffrn_24_27 = *:4 (disp12 + lf_rm_20_23);
}
-# TODO: FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd (disp×8+Rm) → DRn
+# FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd (disp×8+Rm) → DRn
+:fmov.d @(disp12, lf_rm_20_23), lfdrn_25_27
+ is lfop_28_31=0b0011 & lfdrn_25_27 & lfop_24_24=0b0 & lf_rm_20_23 & lfop_12_19=0b00010111 & lfdisp_00_11 & fpscr_sz=0b1
+ [ disp12 = lfdisp_00_11 * 8; ]
+{
+ lfdrn_25_27 = *:8 (disp12 + lf_rm_20_23);
+}
+
# FMOV.S FRm, @( R0,Rn ) 1111nnnnmmmm0111 FRm → (R0+Rn)
-:fmov.s ffrm_04_07, @( r0, f_rn_08_11 ) is r0 & fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b0111
+:fmov.s ffrm_04_07, @( r0, f_rn_08_11 ) is r0 & fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b0111 & fpscr_sz=0b0
{
*:4 (f_rn_08_11 + r0) = ffrm_04_07;
}
-# TODO: FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 DRm → (R0+Rn)
+# FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 DRm → (R0+Rn)
+:fmov.d fdrm_05_07, @( r0, f_rn_08_11 ) is r0 & fop_12_15=0b1111 & f_rn_08_11 & fdrm_05_07 & fop_04_04=0b0 & fop_00_03=0b0111 & fpscr_sz=0b1
+{
+ *:8 (f_rn_08_11 + r0) = fdrm_05_07;
+}
# FMOV.S FRm, @-Rn 1111nnnnmmmm1011 Rn- = 4, FRm → (Rn)
-:fmov.s ffrm_04_07, @-f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1011
+:fmov.s ffrm_04_07, @-f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1011 & fpscr_sz=0b0
{
f_rn_08_11 = f_rn_08_11 - 4;
*:4 (f_rn_08_11) = ffrm_04_07;
}
-# TODO: FMOV.D DRm, @-Rn 1111nnnnmmm01011 Rn- = 8, DRm → (Rn)
+# FMOV.D DRm, @-Rn 1111nnnnmmm01011 Rn- = 8, DRm → (Rn)
+:fmod.s fdrm_05_07, @-f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & fdrm_05_07 & fop_04_04=0b0 & fop_00_03=0b1011 & fpscr_sz=0b1
+{
+ f_rn_08_11 = f_rn_08_11 - 8;
+ *:8 (f_rn_08_11) = fdrm_05_07;
+}
# FMOV.S FRm, @Rn 1111nnnnmmmm1010 FRm → (Rn)
-:fmov.s ffrm_04_07, @f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1010
+:fmov.s ffrm_04_07, @f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1010 & fpscr_sz=0b0
{
*:4 (f_rn_08_11) = ffrm_04_07;
}
-# TODO: FMOV.D DRm, @Rn 1111nnnnmmm01010 DRm → (Rn)
+# FMOV.D DRm, @Rn 1111nnnnmmm01010 DRm → (Rn)
+:fmov.d fdrm_05_07, @f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & fdrm_05_07 & fop_04_04=0b0 & fop_00_03=0b1010 & fpscr_sz=0b1
+{
+ *:8 (f_rn_08_11) = fdrm_05_07;
+}
# FMOV.S FRm, @(disp12,Rn) 0011nnnnmmmm0001 0011dddddddddddd FRm → (disp×4+Rn)
:fmov.s lffrm_20_23, @(disp12, lf_rn_24_27)
- is lfop_28_31=0b0011 & lf_rn_24_27 & lffrm_20_23 & lfop_12_19=0b00010011 & lfdisp_00_11
+ is lfop_28_31=0b0011 & lf_rn_24_27 & lffrm_20_23 & lfop_12_19=0b00010011 & lfdisp_00_11 & fpscr_sz=0b0
[ disp12 = lfdisp_00_11 * 4; ]
{
*:4 (disp12 + lf_rn_24_27) = lffrm_20_23;
}
-# TODO: FMOV.D DRm, @(disp12,Rn) 0011nnnnmmm000010 011dddddddddddd DRm → (disp×8+Rn)
+# FMOV.D DRm, @(disp12,Rn) 0011nnnnmmm000010 011dddddddddddd DRm → (disp×8+Rn)
+:fmov.d lfdrm_21_23, @(disp12, lf_rn_24_27)
+ is lfop_28_31=0b0011 & lf_rn_24_27 & lfdrm_21_23 & lfop_20_20=0b0 & lfop_12_19=0b00010011 & lfdisp_00_11 & fpscr_pr=0b1
+ [ disp12 = lfdisp_00_11 * 8; ]
+{
+ *:8 (disp12 + lf_rn_24_27) = lfdrm_21_23;
+}
# FMUL FRm, FRn 1111nnnnmmmm0010 FRn × FRm → FRn
-:fmul ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0010
+:fmul ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0010 & fpscr_pr=0b0
{
ffrn_08_11 = ffrn_08_11 f* ffrm_04_07;
}
-# TODO: FMUL DRm, DRn 1111nnn0mmm00010 DRn × DRm → DRn
+# FMUL DRm, DRn 1111nnn0mmm00010 DRn × DRm → DRn
+:fmul fdrm_05_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fdrm_05_07 & fop_04_04 = 0b0 & fop_00_03=0b0010 & fpscr_pr=0b1
+{
+ fdrn_09_11 = fdrn_09_11 f* fdrm_05_07;
+}
+
# FNEG FRn 1111nnnn01001101 -FRn → FRn
-:fneg ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01001101
+:fneg ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01001101 & fpscr_pr=0b0
{
ffrn_08_11 = f- ffrn_08_11;
}
-# TODO: FNEG DRn 1111nnn001001101 -DRn → DRn
-# FSCHG 1111001111111101 FPSCR.SZ = ~ FPSCR.SZ
-:fschg is fop_00_15=0b1111001111111101
+# FNEG DRn 1111nnn001001101 -DRn → DRn
+:fneg fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fop_00_07=0b01001101 & fpscr_pr=0b1
{
- $(FP_SZ) = ~ $(FP_SZ);
+ fdrn_09_11 = f- fdrn_09_11;
}
# FSQRT FRn 1111nnnn01101101 √FRn → FRn
-:fsqrt ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01101101
+:fsqrt ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01101101 & fpscr_pr=0b0
{
ffrn_08_11 = sqrt(ffrn_08_11);
}
-# TODO: FSQRT DRn 1111nnn001101101 √DRn → DRn
+# FSQRT DRn 1111nnn001101101 √DRn → DRn
+:fsqrt fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fop_00_07=0b01101101 & fpscr_pr=0b1
+{
+ fdrn_09_11 = sqrt(fdrn_09_11);
+}
+
# FSTS FPUL, FRn 1111nnnn00001101 FPUL → FRn
-:fsts fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00001101
+:fsts fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00001101 & fpscr_pr=0b0 & fpscr_pr=0b0
{
ffrn_08_11 = fpul;
}
# FSUB FRm, FRn 1111nnnnmmmm0001 FRn - FRm → FRn
-:fsub ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0001
+:fsub ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0001 & fpscr_pr=0b0
{
ffrn_08_11 = ffrn_08_11 f- ffrm_04_07;
}
-# TODO: FSUB DRm, DRn 1111nnn0mmm00001 DRn - DRm → DRn
+# FSUB DRm, DRn 1111nnn0mmm00001 DRn - DRm → DRn
+:fsub fdrm_05_07, fdrn_09_11 is fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fdrm_05_07 & fop_04_04 = 0b0 & fop_00_03=0b0001 & fpscr_pr=0b1
+{
+ fdrn_09_11 = fdrn_09_11 f- fdrm_05_07;
+}
# FTRC FRm, FPUL 1111mmmm00111101 (long) FRm → FPUL
-:ftrc ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00111101
+:ftrc ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00111101 & fpscr_pr=0b0
{
fpul = trunc(ffrm_08_11);
}
# FTRC DRm, FPUL 1111mmm000111101 (long) DRm → FPUL
+:ftrc fdrm_09_11, fpul is fpul & fop_12_15=0b1111 & fdrm_09_11 & fop_08_08=0b0 & fop_00_07=0b00111101 & fpscr_pr=0b1
+{
+ fpul = trunc(fdrm_09_11);
+}
@endif
@@ -2211,7 +2300,7 @@ define pcodeop Sleep_Standby;
# LDS Rm,FPSCR 0100mmmm01101010 Rm → FPSCR
:lds rm_08_11, fpscr is fpscr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01101010
{
- fpscr = rm_08_11;
+ fpscr = rm_08_11 & 0x003FFFFF;
}
# LDS Rm,FPUL 0100mmmm01011010 Rm → FPUL
@@ -2223,7 +2312,7 @@ define pcodeop Sleep_Standby;
# LDS.L @Rm+, FPSCR 0100mmmm01100110 (Rm) → FPSCR, Rm+ = 4
:lds.l @rm_08_11+, fpscr is fpscr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01100110
{
- fpscr = *:4 (rm_08_11);
+ fpscr = *:4 (rm_08_11) & 0x003FFFFF;
rm_08_11 = rm_08_11 + 4;
}
@@ -2237,7 +2326,7 @@ define pcodeop Sleep_Standby;
# STS FPSCR, Rn 0000nnnn01101010 FPSCR → Rn
:sts fpscr, rn_08_11 is fpscr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b01101010
{
- rn_08_11 = fpscr;
+ rn_08_11 = fpscr & 0x003FFFFF;
}
# STS FPUL,Rn 0000nnnn01011010 FPUL → Rn
@@ -2250,7 +2339,7 @@ define pcodeop Sleep_Standby;
:sts.l fpscr, @-rn_08_11 is fpscr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b01100010
{
rn_08_11 = rn_08_11 - 4;
- *:4 (rn_08_11) = fpscr;
+ *:4 (rn_08_11) = fpscr & 0x003FFFFF;
}
# STS.L FPUL,@-Rn 0100nnnn01010010 Rn- = 4, FPUL → (Rn)
@@ -2260,7 +2349,11 @@ define pcodeop Sleep_Standby;
*:4 (rn_08_11) = fpul;
}
-# @if defined(FPU)
+# FSCHG 1111001111111101 FPSCR.SZ = ~ FPSCR.SZ
+:fschg is fop_00_15=0b1111001111111101 [ fpscr_sz = fpscr_sz ^ fpscr_pr; globalset(inst_next,fpscr_sz); ]
+{
+}
+
@endif
--
2.45.1