uart_tx.v

// Author: Jatin Ramchandani
`timescale 1ns / 1ps


// You MUST NOT change the module name or the ports declarations

module uart_tx (
        input clk,
        input rst_n,
        input [7:0] data_byte_in,
        input send_now,

        output reg finish_tx,
        output reg uart_tx_o
    );

    // These declarations are provided as hints for a possible implementation.
    // You are free to modify, add, or remove them as long as the module's
    // external behavior is correct

    // FSM states parameters
    localparam INIT = 0,
               SEND = 1,
               DONE = 2;

    reg [1:0] state;

    reg [13:0] baud_time_counter; // counts clock ticks to measure the duration of one bit period
    reg [3:0] bit_counter; // 10 bits for transfering a whole byte

    reg [16:0] wait_between_byte; // counts clock ticks for the wait duration (20000 ycles)

    // ----------- Insert your codes below --------------//
    
    // Timing: 100 MHz clock, 9600 baud
    localparam integer CLKS_PER_BIT = 10417;
    localparam integer WAIT_CYCLE = 20000;
    
    // The following always block was refined with assistance of LLMs
    
    always @(posedge clk or negedge rst_n) begin 
        if(!rst_n) begin
            state <= INIT;
            uart_tx_o <= 1'b1;
            finish_tx <= 1'b0;
            baud_time_counter <= 14'd0;
            bit_counter       <= 4'd0;
            wait_between_byte <= 17'd0;
            
        end else begin
            
            finish_tx <= 1'b0;
                        
            case (state)
            
                INIT: begin
                    if(send_now) begin
                        state <= SEND;
                    end else begin
                        bit_counter <= 4'b0;
                        uart_tx_o <= 1'b1;
                        baud_time_counter <= 14'd0;
                        wait_between_byte <= 17'd0;
                    end
                end
                 
                SEND: begin
                
                    if (baud_time_counter == CLKS_PER_BIT-1) begin
                        baud_time_counter <= 14'd0;
                            if (bit_counter == 4'd9) begin
                                state       <= DONE;
                                bit_counter <= 4'd0;
                            end else begin
                                bit_counter <= bit_counter + 4'd1;
                            end
                    end else begin
                        baud_time_counter <= baud_time_counter + 14'd1;
                    end
                    
                    // The following function block was refined with assistance of LLMs
                                  
                    if (baud_time_counter == CLKS_PER_BIT-1) begin
                                          
                        case (bit_counter)
                            4'd0: begin
                                
                                uart_tx_o <= 1'b0;
                            end
                            
                            4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8: begin
                                 uart_tx_o <= data_byte_in[bit_counter-1];
                            end
                            
                            4'd9: begin
                                 uart_tx_o <= 1'b1;
                            end
                            
                            default: uart_tx_o <= 1'b1; 
                            endcase
                         end 
                   end                  

                DONE: begin
                    
                    uart_tx_o <= 1'b1;
                
                    if(wait_between_byte == WAIT_CYCLE) begin
                        state <= INIT;
                        wait_between_byte <= 17'd0;
                        finish_tx <= 1'b1;
                    end else begin
                        wait_between_byte <= wait_between_byte + 1'b1;
                    end   
                 end    
                    
                default: begin
                    state <= INIT;
                end 
                
                endcase
            end
         end 

endmodule