A 4-layer industrial sensor node for pump and motor monitoring. 24 V field power, two 4–20 mA loop inputs, opto-isolated digital inputs, a relay output, and a galvanically isolated RS-485 / Modbus port to a PLC. ESP32-C6 with Wi-Fi 6 and BLE.
Designed from a blank schematic in KiCad 10 — component selection, schematic capture, layout, and a complete manufacturing package.
| Board | 130 × 100 mm, 4 layers, FR-4 |
| Stack-up | Signal / solid GND / PWR / Signal |
| MCU | ESP32-C6 — Wi-Fi 6, BLE, RISC-V |
| Field power | 24 V DC — fuse, TVS, reverse-polarity FET |
| Rails | TPS54360 buck to 5 V at 400 kHz, LDO to 3.3 V |
| Analog in | 2 × 4–20 mA loops, 150 R 0.1 % shunts into a 16-bit ADS1115 |
| Digital in | 2 × opto-coupled 24 V inputs |
| Output | 1 × SPDT relay |
| Fieldbus | Isolated RS-485 / Modbus — digital isolator, isolated DC-DC, transceiver |
| RF | 50 Ω microstrip to a u.FL antenna connector |
| Design tool | KiCad 10 |
Measured from the board file, not asserted.
| Footprints | 112 |
| Nets | 76 |
| Copper zones | 10 |
| Track segments | 637 |
| Vias | 266 |
| Copper drawn | ≈ 2252 mm |
| ERC | 0 errors, 0 warnings |
| DRC | 0 unconnected, fully routed |
Hierarchical schematic across 5 sheets · fully routed 4-layer PCB · Gerbers (RS-274X) · separate PTH and NPTH Excellon drill files with drill maps and report · pick-and-place · assembly drawing · BOM with a manufacturer part number against every fitted part · 3D STEP model for enclosure fit · fabrication README covering stack-up, impedance spec and assembly notes.
The field side and the logic side are separated by an 8 mm copper-free barrier, with slots routed clean through the board to stretch the creepage path further than the gap alone would give. No copper, no silkscreen, no solder-mask bridge crosses it on any layer.
The slots, seen through all copper layers:
The barrier was drawn correctly and it was still wrong.
The isolated DC-DC converter has its own isolation barrier running across the package, top to bottom. Mine was rotated 90° to the board's. The isolated ground had landed on the non-isolated side — 5 mm from the converter's own input pin.
8 mm of clearance and a 3 kV isolator, both doing nothing, because one part faced the wrong way.
Worse, the creepage measurement I had taken ran along the package's non-isolating axis. It read a comfortable 7.10 mm and meant nothing. The real number was 4.08 mm.
Isolation is not a distance you draw on a board. It is the weakest link in a chain, and the chain includes every component that bridges the gap.
Two more results worth keeping:
- The 0.2104 mm prepreg under the top layer is not a detail. It is the only reason the antenna trace is 50 Ω. If a fab substitutes it quietly the RF stops working, and nothing in the Gerbers tells you why. It is stated in the fab README for that reason.
- Some routing is impossible, and that is information rather than failure. Three signals between the isolator and the transceiver would not fit on one layer at any spacing — the two parts number their pins in opposite order. That is a topology problem, not a placement one.
- 0.36 mm trace on 0.2104 mm prepreg for a 50 Ω antenna feed
- Ten net classes, with custom DRC rules for the isolation barrier, relay creepage and RF
- Worst-case power budget per rail, stated against the ratings of the parts fitted
- Every schematic sheet carries its design rationale, not only its netlist
Five sheets, hierarchical. Each carries the reasoning behind its values — why the TVS clamps at 53 V and not 33 V, why the buck compensation is 5.6k / 22nF / 150pF rather than whatever the tool suggested, why there are two grounds that never meet.
System overview
Sheet 1 — Power. 24 V protection, buck to 5 V, LDO to 3.3 V, with the power budget.
Sheet 2 — MCU. ESP32-C6, USB-C, 50 Ω microstrip to the u.FL antenna.
Sheet 3 — Analog in. Two 4–20 mA loops, 150 R 0.1 % shunts, ADS1115 at 16 bits.
Sheet 4 — Digital I/O. Two opto-coupled 24 V inputs, SPDT relay.
Sheet 5 — Isolated RS-485. The barrier, the isolated supply, the transceiver.
Complete design with a fabrication package ready to send. Not manufactured.
Karim Hossam — Electrical & Electronic Engineer, B.Eng First Class Honours, Coventry University 2026.
Available for PCB design, schematic capture, layout, and design review before fabrication.
© 2026 Karim Hossam. Design files are not published. This repository documents the work.