soc_linux: drive the vexriscv_smp tunneled debug port from BSCANE2 - #458
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soc_linux: drive the vexriscv_smp tunneled debug port from BSCANE2#458disdi wants to merge 1 commit into
disdi wants to merge 1 commit into
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With --with-privileged-debug and without --jtag-tap, the RISC-V DTM is
tunneled: debugPort_* carries a JTAG instruction/data path and expects a
vendor boundary-scan primitive to drive it.
Instantiate BSCANE2 and bind TCK/SEL/CAPTURE/SHIFT/UPDATE/RESET/TDI plus TDO
back to the CPU, so the tunneled DTM reaches the FPGA's own JTAG chain and is
usable over the board's existing USB-JTAG cable.
JTAG_CHAIN=4 selects USER4, whose IR is 0x23d. USER1 is deliberately left free
for jtagbone, which LiteX puts on chain 1, so bus access and CPU debug can share
one cable.
Verified on a Digilent Arty A7-35T over the on-board FT2232, with
./make.py --board=arty --cpu-count=1 --with-privileged-debug:
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, misa=0x40141101
halt/resume with advancing pc, memory read of the reset vector, and GDB
attach with symbols and a multi-frame backtrace on bios.elf.
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With --with-privileged-debug and without --jtag-tap, the RISC-V DTM is tunneled: debugPort_* carries a JTAG instruction/data path and expects a vendor boundary-scan primitive to drive it.
Instantiate BSCANE2 and bind TCK/SEL/CAPTURE/SHIFT/UPDATE/RESET/TDI plus TDO back to the CPU, so the tunneled DTM reaches the FPGA's own JTAG chain and is usable over the board's existing USB-JTAG cable.
JTAG_CHAIN=4 selects USER4, whose IR is 0x23d. USER1 is deliberately left free for jtagbone, which LiteX puts on chain 1, so bus access and CPU debug can share one cable.
Verified on a Digilent Arty A7-35T over the on-board FT2232, with ./make.py --board=arty --cpu-count=1 --with-privileged-debug:
halt/resume with advancing pc, memory read of the reset vector, and GDB attach with symbols and a multi-frame backtrace on bios.elf.