Glitches in LiteSPICSControl

[michael-betz]

litespi/litespi/cscontrol.py

Line 27 in 8ca711b

enable_cond = timer.done | (last_active_cs != cs)

The condition last_active_cs != cs is supposed to override the timer.done signal when a different chip is selected.

However it can only do that for a single clock cycle as shown below ...

This corrupts the output signal pads.cs_n

I guess one could reset the timer when last_active_cs != cs. I'll try that out later.

[enjoy-digital]

Thanks @michael-betz, I confirmed the issue on current master. last_active_cs
was updated on the first bypassed cycle, so the mismatch disappeared while the
delay timer was still pending and CS was deasserted on the following cycle.

I opened #115 with a focused fix. It retains the full previous CS selection and
updates last_active_cs when the transaction ends, which keeps a different-CS
bypass active for the complete transfer. The existing delay remains in effect
when the same chip is selected again. Resetting the timer on the mismatch alone
would not be sufficient because updating last_active_cs would still remove the
bypass on the next cycle.

The new simulations reproduce the reported glitch and cover initial selection,
switching both ways between two chip-selects, and repeated access to the same
chip. The full test suite passes (47 passed, 647 subtests passed). A check on
your original hardware/waveform would also be useful.