RISC-V IEEE 754 Floating point Support

[NLS-04]

Add comprehensive floating-point extension support to RISC-V processor models

This whole PR adds floating-point support to Ripes, enabling simulation of the RISC-V F single-precision floating-point (and Zicsr constrol and status register) extensions. The implementation is modular in design so that future works can build upon this PR.

What is Added

• New RISC-V processors with floating-point support
• Core floating-point integration into ripes (register file, instructions, extensions, isa, assembler etc.)
• New extension handling and managing system for more complex extensions and overall clarity
• New processor registration implementation with a new processor selection GUI, declutering the existing processor selction GUI, grouping processor by a common family or idea (like 5-stage)

The PR consists of 3 major parts:

1. core floating-point integration into Ripes and addition of new floating-point processors
2. overhaul of the ISA extension handling system with a more robust abstraction layer
3. rework of the processor registry, selection dialog and handler to facilitate family-variant relationships (could be possibly segregated into a separate PR)

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1. Core Floating-Point Integration

Impact

• Enables simulation of floating-point workloads on RISC-V processors
• Provides accurate RISC-V and IEEE 754-compliant floating-point behavior
• Improves register file design for extensibility
• Adds foundation for future floating-point integrations, like the D, Q, Zfh extensions etc.

What Changed

Core Components:

• Floating-Point Unit (FPU): Added FPU with support for all standard operations, rounding modes, and exception flags, and fcsr interactions. Added two variants of the FPU:
  • the core FPU, which handles all floating-point operations, delegating them to the softfloat library, managing and synchronizing the internal state of the rounding mode and flags between the softlfoat library and the Simulation;
  • and a wrapper around the core that exposes the internal state via pins to the widget so that the state can be visualized in the processor diagram, as seen in the pictures
• fcsr: floating-point csr as VSRTL Register component inside the FPU for direct access
• Berkeley SoftFloat Integration: Integrated Berkeley SoftFloat library for (RISC-V) IEEE 754-compliant floating-point arithmetic
• Floating-Point & CSR Register Files: Added floating-point and csr register file to ISA
• Sim Components: added updated and extended Decoder, controller and register file components to work with the additions of the F extensions

ISA Extensions:

• F Extension: Added all the Single-precision floating-point instructions and pseudo instructions (FADD.S, FSUB.S, FMUL.S, FDIV.S, etc.)
• Zicsr Extension: Added all Control and Status Register insructions and pseudo instructions

Note

For simplicity the current intergations of the floating-point unit and fcsr avaoid the integration of a dedicated CSR register file and controller by making the fcsr part of the FPU. Therefore, the FPU also manages the state of the fcsr and the acces via the Zicsr instructions.

Processor Models:

• rvss_float: Single-cycle floating-point processor
  
• rv5s_float_no_fw_hz: Five-stage pipeline floating-point processor (no forwarding, no hazard detection)
  

Assembler & Frontend:

• Added floating-point immediate parsing in expression evaluator
• Added .float GNU directive support
• Enhanced syntax highlighting for FP immediates, rounding mode constants, and Zicsr registers
• Improved expression parser for easier extension of epxressions (deviating from a union/variant design to a polymorphism design, as this simplifies the expression parsing definition)
• Correctly added the floating-point register file to the existing register file viewer in the GUI
  

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2. Overhaul of the ISA Extension Handling System

A new extension management system in Ripes is also introduced, replacing the previous string-literal based handling with a typed abstraction interface.
It is built on top of the floating-point integration work and prepares the codebase for cleaner extension composition, dependency handling, and future ISA growth.

The implementation is modular and keeps compatibility with existing processor models while migrating them to the new interface.

Impact

• Replaces brittle extension string handling with a typed and extendable abstraction
• Improves correctness and maintainability of extension enable/disable logic
• Enables explicit extension dependencies (implicated extensions) and canonical ordering
• Creates a robust base for upcoming extension work and non-RISC-V extension models
• Simplifies integration points for processors, CLI, and ISA construction

What Changed

Core Extension System

• Added polymorphic extension interfaces for:
  • extension identity and comparison
  • user-facing metadata
  • compiler march naming
  • extension implication relationships
• Added generic extension-set interface:
  • canonical container behavior
  • recursive extension search
  • subset/equality operations
  • cloning and mutation helpers
• Added ISA registry logic that caches/returns ISA objects by enabled extension set

RISC-V Integration

• Added a dedicated RISC-V extension manager with canonical extension definitions
• Reworked RISC-V ISA base setup to:
  • validate selected extension sets
  • load extension instructions via extension-provided enable hooks
  • generate march strings from extension set contents
• Updated RV32/RV64 ISA constructors and initialization to use extension-set driven setup
• Updated decode/uncompress and processor-side handling to use the new extension type interface

MIPS Integration (just for integrity)

• Adapted MIPS ISA wiring to the new extension-set abstractions

CLI and Runtime Integration

• Updated CLI extension argument validation against the new extension container/search interface
• Updated model startup path to enable selected extensions through the typed system

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3. Rework of the Processor Registry, Selection Dialog and Handler

Additionally, a new processor family-variant management model in Ripes is also integrated, built on top of the floating-point and extension-system work.
Instead of selecting a processor via a flat model list, processors are now organized into families and concrete variants, with unified handling across GUI, CLI, runtime selection, settings, and tests.

This improves clarity for users, reduces duplication in processor registration, and makes adding new processor variants significantly easier.

What Changed

Processor Registry and Model Layer

• Refactored processor registry into processor classes (families) with concrete variations
• Added variation descriptors with:
  • unique variation ID
  • human-readable variation name
  • bit width
  • selectable options
• Added family-level helpers to:
  • list supported bit widths
  • query available variations
  • retrieve default variation
  • resolve variation or fallback to default
• Updated processor descriptions and constructors to use variation-aware interfaces

Processor Selection GUI

• Reworked processor selection dialog and UI flow to:
  • select processor family first
  • filter/select valid variations
  • derive available options/extensions from matching variations
• Improved propagation and validation when selection changes
• Updated related main-window and processor-tab integration points

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New GUI Interface (no conflicting options/extensions selected)

New GUI Interface (F extension not available for the selected options)

New GUI Interface (options not available for the selected F extension)

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Runtime and Handler Integration

• Updated ProcessorHandler to store and operate on both:
  • processor ID
  • variation ID
• Updated processor construction path to use variation-specific descriptions
• Updated register initialization and related flows to align with the selected variation

CLI Integration

• Extended CLI processor selection format to support variation selection:
  • Processor[:Variation]
• Added validation against selected family variations
• Updated extension and register-initialization validation to use selected variation ISA info

Settings and Persistence

• Added variation-related settings state so processor variant selection can be preserved across sessions

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Testing and Quality

• Integrated the comprehensive floating-point instruction assembly tests of the existing testing files for the F extension
• Test reorganization: separated F and D extension tests into dedicated directories
• Added cosimulation support for floating-point operations (cosimulation can now handle multiple register files)
• Migrated tests to the new family-variant design:
  • assembler tests
  • cosimulation tests
  • reverse tests
  • riscv tests
• Updated test setup/helpers to select processor class and variation consistently

[NLS-04]

@mortbopet You have this on your radar?

[mortbopet]

@NLS-04 thank you for the ping... I unfortunately haven't "mustered the courage" to review this PR. While i appreciate the (significant) amount of work you've put into it, it is also a very large PR. I think it'd be easier to convince me to review it if you break it up into a series of atomic PRs (as much as possible, of course).