Heterogeneous Hardware Root-of-Trust (RoT) for RISC-V Microcontrollers

A multi-stage, COTS-based secure boot and attestation architecture designed to retrofit NIST SP 800-193 Platform Firmware Resiliency onto resource-constrained microcontrollers (demonstrated on the CDAC THEJAS32 / VEGA Aries v3 RISC-V SoC) without requiring dedicated on-chip cryptographic accelerators.

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🔒 Intellectual Property & Source Code Availability

Notice: The core FPGA Verilog RTL, internal Gatekeeper firmware, and dynamic Galois LFSR seed derivation algorithms are proprietary and currently part of an active academic publication and intellectual property review.

• Public Contents: System architecture specifications, pre-compiled evaluation bitstreams/binaries, NIST SP 800-193 benchmark results, and the Python host provisioning client (fwtool.py).
• Recruiter / Academic Review: Full source code access, RTL schematics, and live hardware-in-the-loop demonstrations can be provided during technical interviews or upon formal request.

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System Architecture

[ Host Provisioning Client (fwtool.py) ]
                    │
                    ▼ (UART DMA: Version, Payload, Signature, HMAC)
+───────────────────────────────────────────────────────────+
|               STAGE-1: STM32F103 GATEKEEPER               |
|  - Anti-Rollback Protection (Flash Monotonic Counter)     |
|  - Ed25519 Asymmetric Digital Signature Verification     |
+───────────────────────────┬───────────────────────────────+
                            │ SPI (Mode 0)
                            ▼
+───────────────────────────────────────────────────────────+
|             LATTICE iCE40 FPGA SECURE ELEMENT             |
|  - Nested HMAC-SHA256 Hardware Coprocessor Engine         |
|  - Hardware-Isolated 256-Bit Secret Key                   |
+───────────────────────────┬───────────────────────────────+
                            │ 
                            ▼ Dual-Channel Hardware Interlock
+───────────────────────────────────────────────────────────+
|             STAGE-2: CDAC THEJAS32 RISC-V SOC             |
|  - Channel 1: Attested SHA-256 Digest Match (UART)        |
|  - Channel 2: Synchronous Dynamic Galois LFSR (PB0->PIN_2)|
|  - Anti-Jumper & Anti-Replay Hardware Defense             |
+───────────────────────────────────────────────────────────+

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Repository Structure

github/
├── host_tools/                     # Python offline signing & provisioning client
│   ├── fwtool.py                   # Ed25519 signing & UART DMA frame dispatcher
│   ├── public_key.pem              # Public key for payload verification
│   └── README.md                   # Toolchain usage instructions
│
├── precompiled_eval_binaries/      # Pre-built bitstreams & images (IP-protected)
│   ├── ice40_secure_element.bin    # Compiled FPGA hardware bitstream
│   ├── authentic_app_v2.bin        # Authentic signed application binary
│   ├── rollback_test_v1.bin        # Test payload for anti-rollback verification
│   └── tampered_test_app.bin       # Test payload for SHA-256 mismatch detection
│
└── docs/                           # Full architectural reports & test records
    ├── README_End2End.md           # End-to-end integration walkthrough
    ├── archi.md                    # System architecture & hardware interconnects
    ├── defensive.md                # Anti-tamper & timing analysis
    ├── maths.md                    # Galois LFSR & cryptographic formulations
    ├── NIST_REPORT_CARD.md         # NIST SP 800-193 pre-compliance results
    └── attacks.md                  # Empirical attack benchmarks (Case Studies A-E)

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Key Innovations & Technical Highlights

1. Zero Host Silicon Redesign: Retrofits modern cryptographic attestation onto existing, proprietary, or legacy ASICs.
2. Cross-Channel Cryptographically Bound Interlock:
   • Eliminates static wire-jumper attacks on physical authorization lines.
   • The hardware authorization pin streams a 32-bit pseudo-random bitstream generated by matching Galois Linear Feedback Shift Registers ($P(x) = x^{32} + x^{22} + x^2 + x^1 + 1$).
   • The initial seed $S_0$ is derived dynamically from the attested SHA-256 digest: $$S_0 = \left( \bigoplus_{i=0}^7 \text{Word}i(D{\text{attested}}) \right) \oplus \texttt{0x5AA5C33C}$$
   • Bit-for-bit cycle synchronization is clocked over UART strobes, requiring $\ge 30/32$ matching bits.
3. Multi-Stage Physical Trust Isolation:
   • Private signing keys are strictly offline (Ed25519).
   • Secret HMAC keys are isolated in the FPGA hardware fabric.
   • The host RISC-V SoC only executes code if both mathematical digest verification and dynamic hardware pin stream match.

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Empirical Verification & Threat Defense

Threat Scenario	Attack Vector	System Defense	Measured Outcome
Bit-Flip / Code Injection	Malicious binary in SPI Flash	Stage-2 recomputed SHA-256 mismatch	BLOCKED (Boot Refused)
Firmware Downgrade	Flash older authentic v1 image	Stage-1 monotonic flash counter check	BLOCKED (NACK 0x13)
Signature Forgery	Signed with attacker private key	Gatekeeper Ed25519 verification fails	BLOCKED (NACK 0x11)
Static Wire Jumper on PIN_2	Wire tied to 3.3V or GND	Dynamic Galois LFSR check (13/32 match)	BLOCKED (Boot Refused)
Genuine Boot	Valid signed frame	Dual-channel agreement (32/32 match)	BOOT VERIFIED & EXECUTED

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Contact & Code Inquiries

For academic collaboration, recruitment inquiries, or complete source code access for technical evaluation, please contact the author via LinkedIn or GitHub profile contact details.