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3090 lines (3090 loc) · 234 KB
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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="S32K344" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="cb0a0571-31b0-4026-b225-2a0da4ce6ac1" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>S32K344</processor>
<package>S32K344_172HDQFP</package>
<mcu_data>PlatformSDK_S32K3</mcu_data>
<cores selected="M7_0">
<core name="Cortex-M7" id="M7_0" description=""/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<enable_parallel_routing>true</enable_parallel_routing>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/Siul2_Port_Ip_Cfg.c" update_enabled="true"/>
<file path="board/Siul2_Port_Ip_Cfg.h" update_enabled="true"/>
<file path="board/Tspc_Port_Ip_Cfg.c" update_enabled="true"/>
<file path="board/Tspc_Port_Ip_Cfg.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>0.0.0</processor_version>
<pin_labels>
<pin_label pin_num="32" pin_signal="PTA29" label="RED_LED" identifier="RED_LED"/>
<pin_label pin_num="43" pin_signal="PTB19" label="SW3" identifier="SW2;SW;SW3"/>
<pin_label pin_num="73" pin_signal="PTB26" label="SW2" identifier="SW3;SW2"/>
<pin_label pin_num="171" pin_signal="PTA9" label="ADC_POT0" identifier="ADC_POT0"/>
<pin_label pin_num="145" pin_signal="PTA15" label="RX" identifier="RX"/>
<pin_label pin_num="143" pin_signal="PTA16" label="TX" identifier="TX"/>
</pin_labels>
</pins_profile>
<functions_list>
<function name="PortContainer_0_BOARD_InitPeripherals">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>M7_0</coreID>
</options>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.driver.pins" description="Pins initialization requires the PINS Driver in the project." problem_level="2" source="Pins:PortContainer_0_BOARD_InitPeripherals">
<feature name="enabled" evaluation="equal" configuration="M7_0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART6" signal="lpuart6_rx" pin_num="145" pin_signal="PTA15"/>
<pin peripheral="LPUART6" signal="lpuart6_tx" pin_num="143" pin_signal="PTA16">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="eMIOS_2" signal="emios_2_ch_12_h" pin_num="32" pin_signal="PTA29">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="ADC0" signal="adc0_p7" pin_num="171" pin_signal="PTA9"/>
<pin peripheral="WKPU" signal="wkpu, 38" pin_num="43" pin_signal="PTB19">
<pin_features>
<pin_feature name="identifier" value="SW3"/>
<pin_feature name="pullEnable" value="enabled"/>
</pin_features>
</pin>
<pin peripheral="SIUL2" signal="eirq, 13" pin_num="73" pin_signal="PTB26">
<pin_features>
<pin_feature name="identifier" value="SW2"/>
<pin_feature name="pullEnable" value="enabled"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="19.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="generate/include/Clock_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Clock_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/src/Clock_Ip_Cfg.c" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>0.0.0</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: FXOSC_CLK.EXTAL, Clocks tool id: FXOSC_CLK.EXTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.XTAL" description="'External pin' (Pins tool id: FXOSC_CLK.XTAL, Clocks tool id: FXOSC_CLK.XTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: SXOSC_CLK.EXTAL, Clocks tool id: SXOSC_CLK.EXTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.XTAL" description="'External pin' (Pins tool id: SXOSC_CLK.XTAL, Clocks tool id: SXOSC_CLK.XTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="M7_0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="FXOSC_CLK.FXOSC_CLK.outFreq" value="16 MHz" locked="false" enabled="true"/>
<clock_source id="SXOSC_CLK.SXOSC_CLK.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="ADC0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="ADC1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="ADC2_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="AIPS_PLAT_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="AIPS_SLOW_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="BCTU0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="CLKOUT_RUN_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
<clock_output id="CLKOUT_STANDBY_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CMP0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CMP1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CMP2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CORE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="CRC0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="DCM0_CLK.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="DCM_CLK.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="DMAMUX0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="DMAMUX1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD10_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD11_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD12_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD13_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD14_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD15_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD16_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD17_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD18_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD19_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD20_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD21_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD22_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD23_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD24_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD25_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD26_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD27_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD28_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD29_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD2_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD30_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD31_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD3_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD4_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD5_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD6_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD7_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD8_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD9_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EIM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMAC0_RX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMAC0_TS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMAC0_TX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMAC_RX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMAC_TS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMAC_TX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMIOS0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMIOS1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="EMIOS2_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="ERM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FIRCOUT.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN3_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN4_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN5_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCANA_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCANB_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FXOSCOUT.outFreq" value="16 MHz" locked="false" accuracy=""/>
<clock_output id="HSE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="INTM_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="LBIST_CLK.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="LCU0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="LCU1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI3_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI4_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI5_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART10_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART11_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART12_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART13_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART14_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART15_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART3_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART4_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART5_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART6_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART7_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART8_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART9_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="MSCM_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="PIT0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="PIT1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="PIT2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="QSPI0_RAM_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="QSPI0_SFCK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="QSPI0_TX_MEM_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="QSPI_MEM_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="QSPI_SFCK_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="RTC0_CLK.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="RTC_CLK.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="SAI0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="SCS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="SEMA42_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="SIRCOUT.outFreq" value="32 kHz" locked="false" accuracy=""/>
<clock_output id="SIUL2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="STCU0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="STM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="STM1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="STMA_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="STMB_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="SWT0_CLK.outFreq" value="32 kHz" locked="false" accuracy=""/>
<clock_output id="SXOSCOUT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="TEMPSENSE_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="TRGMUX0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="TSENSE0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="WKPU0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CORE_MFD.scale" value="120" locked="true"/>
<setting id="FXOSC_PM" value="Crystal_mode" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV0.scale" value="1" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV0_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV1.scale" value="1" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV1_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV2.scale" value="2" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV2_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV3.scale" value="1" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV3_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV4.scale" value="4" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV4_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV5_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV6.scale" value="1" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV6_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_6.sel" value="N/A" locked="false"/>
<setting id="MC_CGM_MUX_6_DE0" value="Enabled" locked="false"/>
<setting id="MC_CGM_MUX_6_DIV0.scale" value="2" locked="true"/>
<setting id="MODULE_CLOCKS.MC_CGM_AUX3_DIV0.scale" value="2" locked="true"/>
<setting id="MODULE_CLOCKS.MC_CGM_AUX4_DIV0.scale" value="2" locked="true"/>
<setting id="PHI0.scale" value="3" locked="true"/>
<setting id="PHI1.scale" value="3" locked="true"/>
<setting id="PLL_PREDIV.scale" value="2" locked="true"/>
<setting id="PLLunderMcuControl" value="Disabled" locked="false"/>
<setting id="POSTDIV.scale" value="2" locked="true"/>
<setting id="SXOSC_PM" value="Crystal_mode" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<ddr name="DDR" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<components/>
</ddr>
<dcd name="DCD" version="1.0" enabled="false" update_project_code="true" isSelfTest="false">
<generated_project_files/>
<dcdx_profile>
<processor_version>N/A</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcd>
<ivt name="IVT" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<ivt_profile>
<processor_version>N/A</processor_version>
</ivt_profile>
</ivt>
<quadspi name="QuadSPI" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<quadspi_profile>
<processor_version>N/A</processor_version>
</quadspi_profile>
</quadspi>
<efuse name="eFUSE" version="1.0" enabled="false" update_project_code="true">
<efuse_profile>
<processor_version>N/A</processor_version>
</efuse_profile>
</efuse>
<gtm name="GTM" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<gtm_profile>
<processor_version>N/A</processor_version>
</gtm_profile>
</gtm>
<ice name="ICE" version="1.0" enabled="false" update_project_code="true">
<ice_profile>
<processor_version>N/A</processor_version>
</ice_profile>
</ice>
<periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.driver.mcl" description="mcl is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.mcl" description="An unsupported version of the mcl in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.uart" description="Uart is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.uart" description="An unsupported version of the Uart in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.port" description="port is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.port" description="An unsupported version of the port in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="osif is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="An unsupported version of the osif in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.Platform" description="Platform is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.Platform" description="An unsupported version of the Platform in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.mcu" description="Mcu is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.mcu" description="An unsupported version of the Mcu in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.adc" description="adc is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.adc" description="An unsupported version of the adc in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.pwm" description="Pwm is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.pwm" description="An unsupported version of the Pwm in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.dio" description="dio is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.dio" description="An unsupported version of the dio in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.icu" description="Icu is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.icu" description="An unsupported version of the Icu in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
</dependencies>
<generated_project_files>
<file path="board/Siul2_Port_Ip_Cfg.c" update_enabled="true"/>
<file path="board/Siul2_Port_Ip_Cfg.h" update_enabled="true"/>
<file path="board/Tspc_Port_Ip_Cfg.c" update_enabled="true"/>
<file path="board/Tspc_Port_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Adc_Cfg.h" update_enabled="true"/>
<file path="generate/include/Adc_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Adc_Ipw_Cfg.h" update_enabled="true"/>
<file path="generate/include/Adc_Ipw_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Adc_Ipw_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Adc_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Adc_Sar_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Adc_Sar_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Adc_Sar_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Bctu_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Bctu_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Bctu_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/CDD_Mcl_Cfg.h" update_enabled="true"/>
<file path="generate/include/CDD_Mcl_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/CDD_Mcl_PBcfg.h" update_enabled="true"/>
<file path="generate/include/CDD_Uart_Cfg.h" update_enabled="true"/>
<file path="generate/include/CDD_Uart_Defines.h" update_enabled="true"/>
<file path="generate/include/CDD_Uart_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Cache_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Cache_Ip_Cfg_DeviceRegisters.h" update_enabled="true"/>
<file path="generate/include/Clock_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Clock_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Clock_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Cmp_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Cmp_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Cmp_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/DeviceDefinition.h" update_enabled="true"/>
<file path="generate/include/Dio_Cfg.h" update_enabled="true"/>
<file path="generate/include/Dma_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Dma_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Dma_Ip_Cfg_DeviceRegistersV3.h" update_enabled="true"/>
<file path="generate/include/Dma_Ip_Cfg_Devices.h" update_enabled="true"/>
<file path="generate/include/Dma_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Emios_Icu_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Emios_Icu_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Emios_Icu_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Emios_Mcl_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Emios_Mcl_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Emios_Mcl_Ip_Cfg_DeviceRegisters.h" update_enabled="true"/>
<file path="generate/include/Emios_Mcl_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Emios_Pwm_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Emios_Pwm_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Emios_Pwm_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Etpu_Pwm_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Etpu_Pwm_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Etpu_Pwm_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/FlexPwm_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/FlexPwm_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/FlexPwm_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Flexio_Mcl_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Flexio_Mcl_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Flexio_Mcl_Ip_Cfg_DeviceRegisters.h" update_enabled="true"/>
<file path="generate/include/Flexio_Mcl_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Flexio_Pwm_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Flexio_Pwm_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Flexio_Pwm_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Flexio_Uart_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Flexio_Uart_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Flexio_Uart_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Flexio_Uart_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Icu_Cfg.h" update_enabled="true"/>
<file path="generate/include/Icu_Ipw_Cfg.h" update_enabled="true"/>
<file path="generate/include/Icu_Ipw_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Icu_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Igf_Port_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Igf_Port_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/IntCtrl_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/IntCtrl_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Intm_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Intm_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Lcu_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Lcu_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Lcu_Ip_Features.h" update_enabled="true"/>
<file path="generate/include/Lcu_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Lcu_Ip_Regs.h" update_enabled="true"/>
<file path="generate/include/Lpuart_Uart_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Lpuart_Uart_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Lpuart_Uart_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Mcu_Cfg.h" update_enabled="true"/>
<file path="generate/include/Mcu_Ipw_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Mcu_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Mpu_M7_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Mpu_M7_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/OsIf_ArchCfg.h" update_enabled="true"/>
<file path="generate/include/OsIf_Cfg.h" update_enabled="true"/>
<file path="generate/include/Platform_Cfg.h" update_enabled="true"/>
<file path="generate/include/Platform_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Platform_Ipw_Cfg.h" update_enabled="true"/>
<file path="generate/include/Port_Cfg.h" update_enabled="true"/>
<file path="generate/include/Port_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Power_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Power_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Power_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Pwm_Cfg.h" update_enabled="true"/>
<file path="generate/include/Pwm_Ipw_Cfg.h" update_enabled="true"/>
<file path="generate/include/Pwm_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Ram_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Ram_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Ram_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Sdadc_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Sdadc_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Sdadc_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Siul2_Dio_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Siul2_Icu_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Siul2_Icu_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Siul2_Icu_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Siul2_Port_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Siul2_Port_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Soc_Ips.h" update_enabled="true"/>
<file path="generate/include/System_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/System_Ip_CfgDefines.h" update_enabled="true"/>
<file path="generate/include/Trgmux_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Trgmux_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/include/Trgmux_Ip_Cfg_DeviceRegisters.h" update_enabled="true"/>
<file path="generate/include/Trgmux_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Tspc_Port_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Uart_Ipw_Cfg.h" update_enabled="true"/>
<file path="generate/include/Uart_Ipw_PBcfg.h" update_enabled="true"/>
<file path="generate/include/Wkpu_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Wkpu_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Wkpu_Ip_PBcfg.h" update_enabled="true"/>
<file path="generate/include/modules.h" update_enabled="true"/>
<file path="generate/src/Adc_Cfg.c" update_enabled="true"/>
<file path="generate/src/Adc_Ipw_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Adc_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Adc_Sar_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Bctu_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/CDD_Mcl_Cfg.c" update_enabled="true"/>
<file path="generate/src/CDD_Mcl_PBcfg.c" update_enabled="true"/>
<file path="generate/src/CDD_Uart_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Clock_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/Clock_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Cmp_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Dio_Cfg.c" update_enabled="true"/>
<file path="generate/src/Dma_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/Dma_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Emios_Icu_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Emios_Mcl_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Emios_Pwm_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Etpu_Pwm_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/FlexPwm_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Flexio_Mcl_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Flexio_Pwm_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Flexio_Uart_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Icu_Cfg.c" update_enabled="true"/>
<file path="generate/src/Icu_DmaNotification.c" update_enabled="true"/>
<file path="generate/src/Icu_Ipw_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Icu_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Igf_Port_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/IntCtrl_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/Lcu_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/Lcu_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Lpuart_Uart_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Mcu_Cfg.c" update_enabled="true"/>
<file path="generate/src/Mcu_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Mpu_M7_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/OsIf_Cfg.c" update_enabled="true"/>
<file path="generate/src/Platform_Cfg.c" update_enabled="true"/>
<file path="generate/src/Platform_Ipw_Cfg.c" update_enabled="true"/>
<file path="generate/src/Port_Cfg.c" update_enabled="true"/>
<file path="generate/src/Port_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Power_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/Power_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Pwm_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Ram_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/Ram_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Sdadc_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Siul2_Icu_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Siul2_Port_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Trgmux_Ip_Cfg.c" update_enabled="true"/>
<file path="generate/src/Trgmux_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Tspc_Port_Ip_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Uart_Ipw_PBcfg.c" update_enabled="true"/>
<file path="generate/src/Wkpu_Ip_PBcfg.c" update_enabled="true"/>
</generated_project_files>
<peripherals_profile>
<processor_version>0.0.0</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="343d8c09-29ab-44df-a8a2-0e35bf16a60f" called_from_default_init="true" id_prefix="" core="M7_0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="Mcl" uuid="4ed3ab62-3519-4fff-8e9b-7040824092e8" type="Mcl" type_id="Mcl" mode="autosar" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="Mcl">
<setting name="Name" value="Mcl"/>
<struct name="ConfigTimeSupport">
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-POST-BUILD"/>
</struct>
<struct name="MclGeneral">
<setting name="Name" value="MclGeneral"/>
<setting name="MclEnableDemReportErrorStatus" value="false"/>
<setting name="MclEnableDevErrorDetect" value="false"/>
<setting name="Mcl_VersionInfoApi" value="false"/>
<setting name="MclEnableUserModeSupport" value="false"/>
<setting name="MclEnableMultipartitionSupport" value="false"/>
<setting name="MclEnableVirtualAddressMappingSupport" value="false"/>
<struct name="MclDma">
<setting name="Name" value="MclDma"/>
<setting name="MclEnableDma" value="false"/>
</struct>
<struct name="MclCache">
<setting name="Name" value="MclCache"/>
<setting name="MclEnableCache" value="true"/>
</struct>
<struct name="MclTrgMux">
<setting name="Name" value="MclTrgMux"/>
<setting name="MclEnableTrgMux" value="false"/>
</struct>
<struct name="MclEmiosCommon">
<setting name="Name" value="MclEmiosCommon"/>
<setting name="MclEnableEmiosCommon" value="true"/>
</struct>
<struct name="MclFlexioCommon">
<setting name="Name" value="MclFlexioCommon"/>
<setting name="MclEnableFlexioCommon" value="false"/>
</struct>
<struct name="MclLcuConfig">
<setting name="Name" value="MclLcu"/>
<setting name="MclEnableLcu" value="false"/>
<setting name="MclEnableLcuSyncFunc" value="false"/>
<setting name="MclEnableLcuAsyncFunc" value="false"/>
</struct>
</struct>
<struct name="MclConfig">
<setting name="Name" value="MclConfig"/>
<array name="MclVirtualMemorySection">
<struct name="0">
<setting name="Name" value="MclVirtualMemorySection_0"/>
<setting name="MclVirtualAddressStart" value="0"/>
<setting name="MclVirtualAddressEnd" value="0xFF"/>
<setting name="MclPhysicalAddressStart" value="0"/>
<setting name="MclPhysicalAddressEnd" value="0xFF"/>
</struct>
</array>
<array name="dmaLogicInstance_ConfigType">
<struct name="0">
<setting name="Name" value="dmaLogicInstance_ConfigType_0"/>
<setting name="dmaLogicInstance_IdName" value="DMA_LOGIC_INST_0"/>
<setting name="dmaLogicInstance_hwId" value="DMA_IP_HW_INST_0"/>
<setting name="dmaLogicInstance_enDebug" value="false"/>
<setting name="dmaLogicInstance_enRoundRobin" value="false"/>
<setting name="dmaLogicInstance_enHaltAfterError" value="false"/>
<setting name="dmaLogicInstance_enChLinking" value="false"/>
<setting name="dmaLogicInstance_enGlMasterIdReplication" value="false"/>
<setting name="dmaLogicInstance_EcucPartitionRef" value=""/>
</struct>
</array>
<array name="dmaLogicChannel_Type">
<struct name="0">
<setting name="Name" value="dmaLogicChannel_Type_0"/>
<setting name="dmaLogicChannel_LogicName" value="DMA_LOGIC_CH_0"/>
<setting name="dmaLogicChannel_HwInstId" value="DMA_IP_HW_INST_0"/>
<setting name="dmaLogicChannel_HwChId" value="DMA_IP_HW_CH_0"/>
<setting name="dmaLogicChannel_InterruptCallback" value="NULL_PTR"/>
<setting name="dmaLogicChannel_ErrorInterruptCallback" value="NULL_PTR"/>
<setting name="dmaLogicChannel_EcucPartitionRef" value=""/>
<setting name="dmaLogicChannel_EnableGlobalConfig" value="false"/>
<setting name="dmaLogicChannel_EnableTransferConfig" value="false"/>
<setting name="dmaLogicChannel_EnableScatterGather" value="false"/>
<struct name="dmaLogicChannel_ConfigType">
<setting name="Name" value="dmaLogicChannel_ConfigType"/>
<struct name="dmaLogicChannel_GlobalConfigType">
<setting name="Name" value="dmaLogicChannel_GlobalConfigType"/>
<struct name="dmaLogicChannelConfig_GlobalControlType">
<setting name="Name" value="dmaLogicChannelConfig_GlobalControlType"/>
<setting name="dmaGlobalControl_enMasterIdReplication" value="false"/>
<setting name="dmaGlobalControl_enBufferedWrites" value="false"/>
</struct>
<struct name="dmaLogicChannelConfig_GlobalRequestType">
<setting name="Name" value="dmaLogicChannelConfig_GlobalRequestType"/>
<setting name="dmaGlobalRequest_enDmaRequest" value="false"/>
</struct>
<struct name="dmaLogicChannelConfig_GlobalInterruptType">
<setting name="Name" value="dmaLogicChannelConfig_GlobalInterruptType"/>
<setting name="dmaGlobalInterrupt_enDmaErrorInterrupt" value="false"/>
</struct>
<struct name="dmaLogicChannelConfig_GlobalPriorityType">
<setting name="Name" value="dmaLogicChannelConfig_GlobalPriorityType"/>
<setting name="dmaGlobalPriority_GroupPriority" value="DMA_IP_GROUP_PRIO0"/>
<setting name="dmaGlobalPriority_LevelPriority" value="DMA_IP_LEVEL_PRIO0"/>
<setting name="dmaGlobalPriority_enPreemption" value="false"/>
<setting name="dmaGlobalPriority_disPreempt" value="false"/>
</struct>
</struct>
<struct name="dmaLogicChannel_TransferConfigType">
<setting name="Name" value="dmaLogicChannel_TransferConfigType"/>
<struct name="dmaLogicChannelConfig_TransferControlType">
<setting name="Name" value="dmaLogicChannelConfig_TransferControlType"/>
<setting name="dmaLogicChannelConfig_enDmaMajorInterrupt" value="false"/>
<setting name="dmaLogicChannelConfig_enDmaHalfMajorInterrupt" value="false"/>
<setting name="dmaLogicChannelConfig_disDmaAutoHwReq" value="false"/>
<setting name="dmaLogicChannelConfig_enEndOfPacketSignal" value="false"/>
<setting name="dmaLogicChannelConfig_bandwidthControl" value="DMA_IP_BWC_ENGINE_NO_STALL"/>
<setting name="dmaLogicChannelConfig_DestinationStoreAddressType" value=""/>
</struct>
<struct name="dmaLogicChannelConfig_TransferSourceType">
<setting name="Name" value="dmaLogicChannelConfig_TransferSourceType"/>
<setting name="dmaLogicChannelConfig_SourceSignedOffsetType" value="0"/>
<setting name="dmaLogicChannelConfig_SourceLastAddressAdjustmentType" value="0"/>
<setting name="dmaTransferConfig_TransferSizeType" value="DMA_IP_TRANSFER_SIZE_1_BYTE"/>
<setting name="dmaLogicChannelConfig_SourceModuloType" value="0"/>
</struct>
<struct name="dmaLogicChannelConfig_TransferDestinationType">
<setting name="Name" value="dmaLogicChannelConfig_TransferDestinationType"/>
<setting name="dmaLogicChannelConfig_DestinationSignedOffsetType" value="0"/>
<setting name="dmaLogicChannelConfig_DestinationLastAddressAdjustmentType" value="0"/>
<setting name="dmaTransferConfig_TransferSizeType" value="DMA_IP_TRANSFER_SIZE_1_BYTE"/>
<setting name="dmaLogicChannelConfig_DestinationModuloType" value="0"/>
</struct>
<struct name="dmaLogicChannelConfig_TransferMinorLoopType">
<setting name="Name" value="dmaLogicChannelConfig_TransferMinorLoopType"/>
<setting name="dmaLogicChannelConfig_enSourceOffset" value="false"/>
<setting name="dmaLogicChannelConfig_enDestinationOffset" value="false"/>
<setting name="dmaLogicChannelConfig_OffsetValueType" value="0"/>
<setting name="dmaLogicChannelConfig_enMinorLoopLinkCh" value="false"/>
<setting name="dynamic_dmaLogicChannelConfig_MinorLoopLinkChValueType" value="/Mcl/Mcl/MclConfig/dmaLogicChannel_Type_0"/>
<setting name="dmaLogicChannelConfig_MinorLoopSizeType" value="0"/>
</struct>
<struct name="dmaLogicChannelConfig_TransferMajorLoopType">
<setting name="Name" value="dmaLogicChannelConfig_TransferMajorLoopType"/>
<setting name="dmaLogicChannelConfig_enMajorLoopLinkCh" value="false"/>
<setting name="dynamic_dmaLogicChannelConfig_MajorLoopLinkChValueType" value="/Mcl/Mcl/MclConfig/dmaLogicChannel_Type_0"/>
<setting name="dmaLogicChannelConfig_MajorLoopCountType" value="0"/>
</struct>
</struct>
<struct name="dmaLogicChannel_ScatterGatherConfigType">
<setting name="Name" value="dmaLogicChannel_ScatterGatherConfigType"/>
<array name="dmaLogicChannelConfig_ScatterGatherArrayType"/>
</struct>
</struct>
</struct>
</array>
<array name="trgmuxInstaceList">
<struct name="0">
<setting name="Name" value="trgmuxInstaceList_0"/>
<setting name="trgmuxHardwareInstance" value="TRGMUX_IP_HW_INST_0"/>
</struct>
</array>
<array name="trgmuxLogicGroup">
<struct name="0">
<setting name="Name" value="trgmuxLogicGroup_0"/>
<setting name="trgmuxLogicGroupHardwareInstance" value="TRGMUX_IP_HW_INST_0"/>
<setting name="trgmuxLogicGroup_Name" value="TRGMUX_IP_ADC12_0"/>
<setting name="trgmuxLogicGroup_Lock" value="false"/>
<array name="trgmuxLogicTrigger">
<struct name="0">
<setting name="Name" value="trgmuxLogicTrigger_0"/>
<setting name="trgmuxLogicTrigger_Name" value="TRGMUX_LOGIC_GROUP_0_TRIGGER_0"/>
<setting name="trgmuxLogicTrigger_Output" value="TRGMUX_IP_OUTPUT_ADC12_0_EXTRG_NORMAL_CONV"/>
<setting name="trgmuxLogicTrigger_Input" value="TRGMUX_IP_INPUT_LOGIC0_VSS"/>
<setting name="trgmuxLogicTrigger_EcucPartitionRef" value=""/>
</struct>
</array>
</struct>
</array>
<array name="EmiosCommon">
<struct name="0">
<setting name="Name" value="EmiosCommon_0"/>
<setting name="EmiosMclInstances" value="EMIOS_2"/>
<setting name="EmiosMclEnableFreezState" value="false"/>
<setting name="EmiosMclEnableGlobalTimeBase" value="true"/>
<setting name="EmiosMclClkDivVal" value="1"/>
<array name="EmiosCommonEcucPartitionRef"/>
<array name="EmiosMclMasterBus">
<struct name="0">
<setting name="Name" value="EMIOS_0_MasteBus0"/>
<setting name="EmiosMclMasterBusNumber" value="EMIOS_CH_23"/>
<setting name="EmiosMclMasterBusModeType" value="MCB_UP_COUNTER"/>
<setting name="EmiosMclDefaultPeriod" value="65534"/>
<setting name="EmiosMclFirstOffsetValue" value="0"/>
<setting name="EmiosMclMasterBusPrescaler" value="DIV_1"/>
<setting name="EmiosMclMasterBusAltPrescaler" value="DIV_1"/>
<setting name="EmiosMclChannelAllowDebugMode" value="true"/>
<setting name="EmiosMclPwmExclusiveAccess" value="true"/>
</struct>
</array>
</struct>
</array>
<array name="FlexioCommon">
<struct name="0">
<setting name="Name" value="FlexioCommon_0"/>
<setting name="FlexioMclInstances" value="FLEXIO_0"/>
<setting name="FlexioDebugEnable" value="false"/>
<array name="FlexioMclLogicChannels">
<struct name="0">
<setting name="Name" value="UART_TX"/>
<setting name="FlexioMclChannelId" value="CHANNEL_0"/>
<setting name="FlexioMclPinId" value="PIN_0"/>
<setting name="FlexioMclAddPinEnable" value="false"/>
<setting name="FlexioMclAddPinId" value="PIN_0"/>
<setting name="FlexioMclAddChannelEnable" value="false"/>
<setting name="FlexioMclAddChannelId" value="CHANNEL_0"/>
</struct>
<struct name="1">
<setting name="Name" value="UART_RX"/>
<setting name="FlexioMclChannelId" value="CHANNEL_1"/>
<setting name="FlexioMclPinId" value="PIN_1"/>
<setting name="FlexioMclAddPinEnable" value="false"/>
<setting name="FlexioMclAddPinId" value="PIN_0"/>
<setting name="FlexioMclAddChannelEnable" value="false"/>
<setting name="FlexioMclAddChannelId" value="CHANNEL_0"/>
</struct>
</array>
</struct>
</array>
<array name="lcuConfiguration">
<struct name="0">
<setting name="Name" value="lcuConfiguration"/>
<array name="lcuInstanceCfg">
<struct name="0" quick_selection="logicCell_default">
<setting name="Name" value="lcuInstanceCfg_0"/>
<setting name="lcuLogicInstance_LogicName" value="LCU_LOGIC_INSTANCE_0"/>
<setting name="lcuLogicInstance_HwInstID" value="LCU_IP_HW_INST_0"/>
<setting name="lcuLogicInstance_OperationMode" value="INTERRUPT"/>
<setting name="lcuLogicCell_UsingForceSignal" value="false"/>
<setting name="lcuLogicCell_UsingSyncSignal" value="false"/>
<array name="lcuLogicCellCfg_lst">
<struct name="0">
<setting name="Name" value="lcuLogicCellCfg_lst_0"/>
<setting name="lcuLogicCell_HwLcID" value="LCU_IP_HW_LC_0"/>
<setting name="lcuLogicCell_EcucPartitionRef" value=""/>
<setting name="lcuLogicCell_forceFilter" value="0"/>
<setting name="lcuLogicCell_usingCombinationalForcePath" value="false"/>
<setting name="lcuLogicCell_usingForcePolarity" value="false"/>
<setting name="lcuLogicCell_SwSyncSel" value="LCU_IP_SYNC_SEL_INPUT0"/>
<setting name="lcuLogicCell_SwOverrideMode" value="LCU_IP_SW_SYNC_IMMEDIATE"/>
<array name="lcuLogicCell_ForceSignalCfg">
<struct name="0">
<setting name="Name" value="lcuLogicCell_ForceSignalCfg_0"/>
<setting name="lcuLogicCell_ForceSignalSelect" value="LCU_IP_FORCE_SEL_INPUT0"/>
<setting name="lcuLogicCell_combEnable" value="false"/>
<setting name="lcuLogicCell_forcePol" value="false"/>
</struct>
</array>
</struct>
</array>
</struct>
</array>
<array name="mclLcuInputConfiguration">
<struct name="0">
<setting name="Name" value="mclLcuInputConfiguration_0"/>
<setting name="lcuLogicInput_LogicName" value="LCU_LOGIC_INPUT_0"/>
<setting name="lcuLogicInput_HwInstID" value="LCU_IP_HW_INST_0"/>
<setting name="lcuLogicInput_HwLcID" value="LCU_IP_HW_LC_0"/>
<setting name="lcuLogicInput_HwInputID" value="LCU_IP_HW_INPUT_0"/>
<setting name="lcuLogicInput_MuxSelect" value="LCU_IP_MUX_SEL_LOGIC_0"/>
<setting name="lcuLogicInput_UsingSwOverride" value="false"/>
<setting name="lcuLogicInput_SwOverrideValue" value="LCU_IP_SW_OVERRIDE_LOGIC_LOW"/>
</struct>
</array>
<array name="mclLcuOutputConfiguration">
<struct name="0">
<setting name="Name" value="mclLcuOutputConfiguration_0"/>
<setting name="lcuLogicOutput_LogicName" value="LCU_LOGIC_OUTPUT_0"/>
<setting name="lcuLogicOutput_HwInstID" value="LCU_IP_HW_INST_0"/>
<setting name="lcuLogicOutput_HwLcID" value="LCU_IP_HW_LC_0"/>
<setting name="lcuLogicOutput_HwOutputID" value="LCU_IP_HW_OUTPUT_0"/>
<setting name="lcuLogicOutput_LutControl" value="0"/>
<setting name="lcuLogicOutput_LutRiseFilter" value="0"/>
<setting name="lcuLogicOutput_LutFallFilter" value="0"/>
<setting name="lcuLogicOutput_InterruptCallback" value="NULL_PTR"/>
<setting name="lcuLogicOutput_DebugMode" value="false"/>
<setting name="lcuLogicOutput_InvertOutput" value="false"/>
<setting name="lcuLogicOutput_LutDmaEnable" value="false"/>
<setting name="lcuLogicOutput_LutIntEnable" value="false"/>
<setting name="lcuLogicOutput_UsingForceSignal" value="false"/>
<struct name="lcuLogicOutput_ForceSignalConfiguration">
<setting name="Name" value="lcuLogicOutput_ForceSignalConfiguration"/>
<setting name="lcuLogicOutput_ForceClearMode" value="LCU_IP_CLEAR_FORCE_SIGNAL_IMMEDIATE"/>
<setting name="lcuLogicOutput_ForceSyncSelect" value="LCU_IP_SYNC_SEL_INPUT0"/>
<setting name="lcuLogicOutput_ForceDmaEnable" value="false"/>
<setting name="lcuLogicOutput_ForceIntEnable" value="false"/>
<array name="lcuLogicOutput_ForceSignalSelect">
<struct name="0">
<setting name="Name" value="lcuLogicOutput_ForceSignalSelect_0"/>
<setting name="lcuLogicOutput_ForceSignal" value="LCU_IP_FORCE_SEL_INPUT0"/>
<setting name="lcuLogicOutput_ForceSignalAffect" value="false"/>
</struct>
</array>
</struct>
</struct>
</array>
</struct>
</array>
</struct>
<struct name="CommonPublishedInformation">
<setting name="Name" value="CommonPublishedInformation"/>
</struct>
</config_set>
</instance>
<instance name="Uart" uuid="96decc69-425e-4b79-b7d4-9ab4586b8973" type="Uart" type_id="Uart" mode="autosar" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="Uart">
<setting name="Name" value="Uart"/>
<struct name="ConfigTimeSupport">
<setting name="POST_BUILD_VARIANT_USED" value="true"/>
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
</struct>
<struct name="GeneralConfiguration">
<setting name="Name" value="GeneralConfiguration"/>
<setting name="UartDevErrorDetect" value="true"/>
<setting name="DisableUartRuntimeErrorDetect" value="false"/>
<setting name="UartMultipartitionSupport" value="false"/>
<setting name="UartEnableUserModeSupport" value="false"/>
<setting name="UartTimeoutMethod" value="OSIF_COUNTER_DUMMY"/>
<setting name="UartTimeoutDuration" value="10000000"/>
<setting name="UartDmaEnable" value="false"/>
<setting name="UartVersionInfoApi" value="false"/>
<array name="UartEcucPartitionRef"/>
<setting name="UartCallbackCapability" value="false"/>
<array name="UartCallback">
<setting name="0" value=""/>
</array>
</struct>
<struct name="UartGlobalConfig">
<setting name="Name" value="UartGlobalConfig"/>
<array name="UartChannel">
<struct name="0">
<setting name="Name" value="LPUART6"/>
<setting name="UartHwUsing" value="LPUART_IP"/>
<setting name="UartChannelId" value="0"/>
<setting name="UartClockRef" value="/Mcu/Mcu/McuModuleConfiguration/McuClockSettingConfig_0/LPUART_CLK"/>
<array name="UartChannelEcucPartitionRef"/>
<struct name="DetailModuleConfiguration">
<setting name="Name" value="DetailModuleConfiguration"/>
<setting name="UartHwChannel" value="LPUART_6"/>
<setting name="DesireBaudrate" value="LPUART_UART_BAUDRATE_115200"/>
<setting name="CustomBaudrateMantissa" value="1"/>
<setting name="CustomBaudrateDivisor" value="4"/>
<setting name="UartInteruptDmaMethod" value="LPUART_UART_IP_USING_INTERRUPTS"/>
<array name="UartDmaTxChannelRef"/>
<array name="UartDmaRxChannelRef"/>
<setting name="UartParityType" value="LPUART_UART_IP_PARITY_DISABLED"/>
<setting name="UartStopBitNumber" value="LPUART_UART_IP_ONE_STOP_BIT"/>
<setting name="UartWordLength" value="LPUART_UART_IP_8_BITS_PER_CHAR"/>
<setting name="UartInternalLoopbackEnable" value="false"/>
<setting name="UartTimeoutEnable" value="false"/>
</struct>
<struct name="FlexioModuleConfiguration">
<setting name="Name" value="FlexioModuleConfiguration"/>
<setting name="UartHwChannelRef" value="/Mcl/Mcl/MclConfig/FlexioCommon_0/FlexioMclLogicChannels_0"/>
<setting name="FlexioUartInteruptDmaMethod" value="FLEXIO_UART_IP_DRIVER_TYPE_INTERRUPTS"/>
<array name="FlexioDmaChannelRef"/>
<setting name="DesireBaudrate" value="FLEXIO_UART_BAUDRATE_9600"/>
<setting name="CustomTimerDecrement" value="FLEXIO_TIMER_DECREMENT_FXIO_CLK_SHIFT_TMR"/>
<setting name="CustomBaudrateDivider" value="0"/>
<setting name="bitCount" value="FLEXIO_UART_IP_8_BITS_PER_CHAR"/>
<setting name="driverDirection" value="FLEXIO_UART_IP_DIRECTION_TX"/>
</struct>
</struct>
</array>