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Copy pathFRDM_A_S32K312_Epaper_Battery_Display.mex
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691 lines (691 loc) · 48.4 KB
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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="S32K312" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="cb0a0571-31b0-4026-b225-2a0da4ce6ac1" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>S32K312</processor>
<package>S32K312_172HDQFP</package>
<mcu_data>PlatformSDK_S32K3</mcu_data>
<cores selected="M7_0">
<core name="Cortex-M7" id="M7_0" description=""/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<enable_parallel_routing>true</enable_parallel_routing>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/Siul2_Port_Ip_Cfg.c" update_enabled="true"/>
<file path="board/Siul2_Port_Ip_Cfg.h" update_enabled="true"/>
<file path="board/Tspc_Port_Ip_Cfg.c" update_enabled="true"/>
<file path="board/Tspc_Port_Ip_Cfg.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>0.0.0</processor_version>
<pin_labels>
<pin_label pin_num="135" pin_signal="PTA1" label="DC" identifier="DC"/>
<pin_label pin_num="121" pin_signal="PTD2" label="BSY" identifier="BSY"/>
<pin_label pin_num="110" pin_signal="PTB17" label="CS" identifier="CS"/>
<pin_label pin_num="172" pin_signal="PTA8" label="RST" identifier="RST"/>
</pin_labels>
</pins_profile>
<functions_list>
<function name="PortContainer_0_BOARD_InitPeripherals">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>M7_0</coreID>
</options>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.driver.pins" description="Pins initialization requires the PINS Driver in the project." problem_level="2" source="Pins:PortContainer_0_BOARD_InitPeripherals">
<feature name="enabled" evaluation="equal" configuration="M7_0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="SIUL2" signal="gpio, 1" pin_num="135" pin_signal="PTA1">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="InitValue" value="state_0"/>
</pin_features>
</pin>
<pin peripheral="LPSPI1" signal="lpspi1_sck" pin_num="114" pin_signal="PTB14">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="LPSPI1" signal="lpspi1_sout" pin_num="112" pin_signal="PTB16">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="SIUL2" signal="gpio, 49" pin_num="110" pin_signal="PTB17">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="InitValue" value="state_0"/>
</pin_features>
</pin>
<pin peripheral="SIUL2" signal="gpio, 98" pin_num="121" pin_signal="PTD2">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="pullSelect" value="pullUp"/>
<pin_feature name="pullEnable" value="enabled"/>
<pin_feature name="InitValue" value="state_1"/>
</pin_features>
</pin>
<pin peripheral="SIUL2" signal="gpio, 8" pin_num="172" pin_signal="PTA8">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="InitValue" value="state_0"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="19.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="generate/include/Clock_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Clock_Ip_Cfg_Defines.h" update_enabled="true"/>
<file path="generate/src/Clock_Ip_Cfg.c" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>0.0.0</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="ClockConfig0" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: FXOSC_CLK.EXTAL, Clocks tool id: FXOSC_CLK.EXTAL) needs to be routed" problem_level="1" source="Clocks:ClockConfig0">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.XTAL" description="'External pin' (Pins tool id: FXOSC_CLK.XTAL, Clocks tool id: FXOSC_CLK.XTAL) needs to be routed" problem_level="1" source="Clocks:ClockConfig0">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: SXOSC_CLK.EXTAL, Clocks tool id: SXOSC_CLK.EXTAL) needs to be routed" problem_level="1" source="Clocks:ClockConfig0">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.XTAL" description="'External pin' (Pins tool id: SXOSC_CLK.XTAL, Clocks tool id: SXOSC_CLK.XTAL) needs to be routed" problem_level="1" source="Clocks:ClockConfig0">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:ClockConfig0">
<feature name="enabled" evaluation="equal" configuration="M7_0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="FXOSC_CLK.FXOSC_CLK.outFreq" value="16 MHz" locked="false" enabled="true"/>
<clock_source id="SXOSC_CLK.SXOSC_CLK.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="ADC0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="ADC1_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="AIPS_PLAT_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="AIPS_SLOW_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="BCTU0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="CLKOUT_RUN_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
<clock_output id="CLKOUT_STANDBY_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CMP0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="CMP1_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="CORE_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="CRC0_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="DCM0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="DCM_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="DMAMUX0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="DMAMUX1_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD10_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD11_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD1_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD2_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD3_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD4_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD5_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD6_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD7_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD8_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EDMA0_TCD9_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EIM0_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="EMIOS0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="EMIOS1_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="ERM0_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="FIRCOUT.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN1_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN3_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN4_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCAN5_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCANA_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXCANB_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="FXOSCOUT.outFreq" value="16 MHz" locked="false" accuracy=""/>
<clock_output id="HSE_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="INTM_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LCU0_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="LCU1_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C1_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI0_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI1_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI2_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI3_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART0_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART1_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART2_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART3_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART4_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART5_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART6_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="LPUART7_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="MSCM_CLK.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="PIT0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="PIT1_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="PLL_PHI0.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="PLL_PHI1.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="RTC0_CLK.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="RTC_CLK.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="SCS_CLK.outFreq" value="120 MHz" locked="false" accuracy=""/>
<clock_output id="SIRCOUT.outFreq" value="32 kHz" locked="false" accuracy=""/>
<clock_output id="SIUL2_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="STCU0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="STM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="STMA_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="SWT0_CLK.outFreq" value="32 kHz" locked="false" accuracy=""/>
<clock_output id="SXOSCOUT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="TEMPSENSE_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="TRGMUX0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TSENSE0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="WKPU0_CLK.outFreq" value="30 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CORE_MFD.scale" value="120" locked="true"/>
<setting id="CORE_PLLODIV_0_DE" value="Enabled" locked="false"/>
<setting id="CORE_PLLODIV_1_DE" value="Enabled" locked="false"/>
<setting id="CORE_PLL_PD" value="Power_up" locked="false"/>
<setting id="FXOSC_PM" value="Crystal_mode" locked="false"/>
<setting id="MC_CGM_MUX_0.sel" value="PHI0" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV0.scale" value="1" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV0_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV1.scale" value="2" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV1_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV2.scale" value="4" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV2_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV3.scale" value="2" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV3_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_0_DIV4.scale" value="4" locked="true"/>
<setting id="MC_CGM_MUX_0_DIV4_Trigger" value="Common" locked="false"/>
<setting id="MC_CGM_MUX_6.sel" value="N/A" locked="false"/>
<setting id="MC_CGM_MUX_6_DE0" value="Enabled" locked="false"/>
<setting id="MC_CGM_MUX_6_DIV0.scale" value="2" locked="true"/>
<setting id="MODULE_CLOCKS.MC_CGM_AUX3_DIV0.scale" value="2" locked="true"/>
<setting id="MODULE_CLOCKS.MC_CGM_AUX4_DIV0.scale" value="2" locked="true"/>
<setting id="PHI0.scale" value="2" locked="true"/>
<setting id="PHI1.scale" value="5" locked="true"/>
<setting id="PLL_PREDIV.scale" value="2" locked="true"/>
<setting id="POSTDIV.scale" value="4" locked="true"/>
<setting id="SXOSC_PM" value="Crystal_mode" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<ddr name="DDR" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<components/>
</ddr>
<dcd name="DCD" version="1.0" enabled="false" update_project_code="true" isSelfTest="false">
<generated_project_files/>
<dcdx_profile>
<processor_version>N/A</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcd>
<ivt name="IVT" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<ivt_profile>
<processor_version>N/A</processor_version>
</ivt_profile>
</ivt>
<quadspi name="QuadSPI" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<quadspi_profile>
<processor_version>N/A</processor_version>
</quadspi_profile>
</quadspi>
<efuse name="eFUSE" version="1.0" enabled="false" update_project_code="true">
<efuse_profile>
<processor_version>N/A</processor_version>
</efuse_profile>
</efuse>
<gtm name="GTM" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<gtm_profile>
<processor_version>N/A</processor_version>
</gtm_profile>
</gtm>
<ice name="ICE" version="1.0" enabled="false" update_project_code="true">
<ice_profile>
<processor_version>N/A</processor_version>
</ice_profile>
</ice>
<periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="osif is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="An unsupported version of the osif in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_port" description="siul2_port is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_port" description="An unsupported version of the siul2_port in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.lpspi" description="Lpspi is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.lpspi" description="An unsupported version of the Lpspi in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_dio" description="siul2_dio is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_dio" description="An unsupported version of the siul2_dio in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.Clock_Ip_ReferencePoints" description="Clock_Ip_ReferencePoints is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data type="Boolean">true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.driver.Clock_Ip_ReferencePoints" description="An unsupported version of the Clock_Ip_ReferencePoints in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
<feature name="version" evaluation="equivalent">
<data type="Version">1.0.0</data>
</feature>
</dependency>
<dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals">
<feature name="enabled" evaluation="equal">
<data>true</data>
</feature>
</dependency>
</dependencies>
<generated_project_files>
<file path="generate/include/DeviceDefinition.h" update_enabled="true"/>
<file path="generate/include/Lpspi_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Lpspi_Ip_Sa_PBcfg.h" update_enabled="true"/>
<file path="generate/include/OsIf_ArchCfg.h" update_enabled="true"/>
<file path="generate/include/OsIf_Cfg.h" update_enabled="true"/>
<file path="generate/include/Siul2_Dio_Ip_Cfg.h" update_enabled="true"/>
<file path="generate/include/Siul2_Port_Ip_Defines.h" update_enabled="true"/>
<file path="generate/include/Soc_Ips.h" update_enabled="true"/>
<file path="generate/include/modules.h" update_enabled="true"/>
<file path="generate/src/Lpspi_Ip_Sa_PBcfg.c" update_enabled="true"/>
<file path="generate/src/OsIf_Cfg.c" update_enabled="true"/>
</generated_project_files>
<peripherals_profile>
<processor_version>0.0.0</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="1e09dc9c-356f-48b5-869e-715ac7e7c55a" called_from_default_init="true" id_prefix="" core="M7_0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="BaseNXP" uuid="ffe9c125-2622-4dc9-b3a9-3bfa63927c4b" type="BaseNXP" type_id="Base" mode="general" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="BaseNXP">
<setting name="Name" value="BaseNXP"/>
<struct name="ConfigTimeSupport">
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
</struct>
<struct name="OsIfGeneral">
<setting name="Name" value="OsIfGeneral"/>
<setting name="OsIfMulticoreSupport" value="false"/>
<setting name="OsIfEnableUserModeSupport" value="false"/>
<setting name="OsIfDevErrorDetect" value="true"/>
<setting name="OsIfUseSystemTimer" value="true"/>
<setting name="OsIfUseCustomTimer" value="false"/>
<setting name="OsIfUseGetUserId" value="GET_CORE_ID"/>
<setting name="OsIfInstanceId" value="255"/>
<setting name="OsIfGetPhysicalCoreIdEnable" value="false"/>
<setting name="OsIfSoftwareSemaphoredEnable" value="false"/>
<struct name="OsIfOperatingSystemType">
<setting name="Name" value="OsIfOperatingSystemType"/>
<setting name="Choice" value="OsIfBaremetalType"/>
<struct name="OsIfBaremetalType" quick_selection="Default">
<setting name="Name" value="OsIfOperatingSystemType"/>
</struct>
</struct>
<array name="OsIfEcucPartitionRef"/>
<array name="OsIfCounterConfig">
<struct name="0">
<setting name="Name" value="OsIfCounterConfig_0"/>
<array name="OsIfCounterEcucPartitionRef"/>
<array name="OsIfSystemTimerClockRef">
<setting name="0" value="/Clock_Ip_ReferencePoints/Clock_Ip_ReferencePoints/CORE_CLK"/>
</array>
<array name="OsIfSystemTimerClockFreq"/>
<array name="OsIfOsCounterRef"/>
</struct>
</array>
</struct>
<struct name="CommonPublishedInformation" quick_selection="Default">
<setting name="Name" value="CommonPublishedInformation"/>
<setting name="ModuleId" value="0"/>
<setting name="VendorId" value="43"/>
<array name="VendorApiInfix"/>
<setting name="ArReleaseMajorVersion" value="4"/>
<setting name="ArReleaseMinorVersion" value="7"/>
<setting name="ArReleaseRevisionVersion" value="0"/>
<setting name="SwMajorVersion" value="5"/>
<setting name="SwMinorVersion" value="0"/>
<setting name="SwPatchVersion" value="0"/>
</struct>
</config_set>
</instance>
<instance name="Siul2_Port" uuid="024e57ff-7bae-4b30-9d96-6777edacc8f9" type="Siul2_Port" type_id="Siul2_Port" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="Siul2_Port">
<setting name="Name" value="Siul2_Port"/>
<struct name="ConfigTimeSupport">
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
</struct>
<struct name="PortGeneral">
<setting name="Name" value="PortGeneral"/>
<setting name="SIUL2PortIPDevErrorDetect" value="true"/>
<setting name="PortEnableUserModeSupport" value="false"/>
</struct>
<struct name="PortConfigSet">
<setting name="Name" value="PortConfigSet"/>
<array name="PortContainer">
<struct name="0">
<setting name="Name" value="PortContainer_0"/>
<array name="PortPin">
<struct name="0">
<setting name="Name" value="PortPin_0"/>
<setting name="PortPinPue" value="false"/>
<setting name="PortPinPus" value="false"/>
<setting name="PortPinSafeMode" value="false"/>
<setting name="PortPinDse" value="false"/>
<setting name="PortPinWithReadBack" value="false"/>
<setting name="PortPinPke" value="false"/>
<setting name="PortPinIfe" value="false"/>
<setting name="PortPinDirectionChangeable" value="true"/>
<setting name="PortPinModeChangeable" value="true"/>
<setting name="PortPinInvertControl" value="false"/>
<setting name="PortPinSiul2Instance" value="SIUL2_0"/>
<setting name="PortPinId" value="1"/>
<setting name="PortPinInitialMode" value="PORT_GPIO_MODE"/>
</struct>
<struct name="1">
<setting name="Name" value="PortPin_1"/>
<setting name="PortPinPue" value="false"/>
<setting name="PortPinPus" value="false"/>
<setting name="PortPinSafeMode" value="false"/>
<setting name="PortPinDse" value="false"/>
<setting name="PortPinWithReadBack" value="false"/>
<setting name="PortPinPke" value="false"/>
<setting name="PortPinIfe" value="false"/>
<setting name="PortPinDirectionChangeable" value="true"/>
<setting name="PortPinModeChangeable" value="true"/>
<setting name="PortPinInvertControl" value="false"/>
<setting name="PortPinSiul2Instance" value="SIUL2_0"/>
<setting name="PortPinId" value="2"/>
<setting name="PortPinInitialMode" value="PORT_GPIO_MODE"/>
</struct>
<struct name="2">
<setting name="Name" value="PortPin_2"/>
<setting name="PortPinPue" value="false"/>
<setting name="PortPinPus" value="false"/>
<setting name="PortPinSafeMode" value="false"/>
<setting name="PortPinDse" value="false"/>
<setting name="PortPinWithReadBack" value="false"/>
<setting name="PortPinPke" value="false"/>
<setting name="PortPinIfe" value="false"/>
<setting name="PortPinDirectionChangeable" value="true"/>
<setting name="PortPinModeChangeable" value="true"/>
<setting name="PortPinInvertControl" value="false"/>
<setting name="PortPinSiul2Instance" value="SIUL2_0"/>
<setting name="PortPinId" value="3"/>
<setting name="PortPinInitialMode" value="PORT_GPIO_MODE"/>
</struct>
<struct name="3">
<setting name="Name" value="PortPin_3"/>
<setting name="PortPinPue" value="false"/>
<setting name="PortPinPus" value="false"/>
<setting name="PortPinSafeMode" value="false"/>
<setting name="PortPinDse" value="false"/>
<setting name="PortPinWithReadBack" value="false"/>
<setting name="PortPinPke" value="false"/>
<setting name="PortPinIfe" value="false"/>
<setting name="PortPinDirectionChangeable" value="true"/>
<setting name="PortPinModeChangeable" value="true"/>
<setting name="PortPinInvertControl" value="false"/>
<setting name="PortPinSiul2Instance" value="SIUL2_0"/>
<setting name="PortPinId" value="4"/>
<setting name="PortPinInitialMode" value="PORT_GPIO_MODE"/>
</struct>
<struct name="4">
<setting name="Name" value="PortPin_4"/>
<setting name="PortPinPue" value="true"/>
<setting name="PortPinPus" value="true"/>
<setting name="PortPinSafeMode" value="false"/>
<setting name="PortPinDse" value="false"/>
<setting name="PortPinWithReadBack" value="false"/>
<setting name="PortPinPke" value="false"/>
<setting name="PortPinIfe" value="false"/>
<setting name="PortPinDirectionChangeable" value="true"/>
<setting name="PortPinModeChangeable" value="true"/>
<setting name="PortPinInvertControl" value="false"/>
<setting name="PortPinSiul2Instance" value="SIUL2_0"/>
<setting name="PortPinId" value="5"/>
<setting name="PortPinInitialMode" value="PORT_GPIO_MODE"/>
</struct>
<struct name="5">
<setting name="Name" value="PortPin_5"/>
<setting name="PortPinPue" value="false"/>
<setting name="PortPinPus" value="false"/>
<setting name="PortPinSafeMode" value="false"/>
<setting name="PortPinDse" value="false"/>
<setting name="PortPinWithReadBack" value="false"/>
<setting name="PortPinPke" value="false"/>
<setting name="PortPinIfe" value="false"/>
<setting name="PortPinDirectionChangeable" value="true"/>
<setting name="PortPinModeChangeable" value="true"/>
<setting name="PortPinInvertControl" value="false"/>
<setting name="PortPinSiul2Instance" value="SIUL2_0"/>
<setting name="PortPinId" value="6"/>
<setting name="PortPinInitialMode" value="PORT_GPIO_MODE"/>
</struct>
</array>
</struct>
</array>
</struct>
</config_set>
</instance>
<instance name="Lpspi" uuid="adc554bb-c899-4bf2-8b8a-3bf610860075" type="Lpspi" type_id="Lpspi" mode="lpspi" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="Lpspi">
<setting name="Name" value="Lpspi"/>
<struct name="ConfigTimeSupport" quick_selection="Default">
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
</struct>
<struct name="SpiDriver">
<setting name="Name" value="SpiDriver"/>
<array name="SpiExternalDevice">
<struct name="0">
<setting name="Name" value="SpiExternalDevice_0"/>
<setting name="SpiBaudrate" value="2000000"/>
<setting name="SpiUseBaudrateConfig" value="false"/>
<array name="SpiBaudrateConfigRef"/>
<setting name="SpiCsIdentifier" value="PCS0"/>
<setting name="SpiCsPolarity" value="LOW"/>
<setting name="SpiDataShiftEdge" value="TRAILING"/>
<setting name="SpiHwUnit" value="CSIB0"/>
<setting name="SpiShiftClockIdleLevel" value="LOW"/>
<setting name="SpiDataWidth" value="8"/>
<setting name="SpiDefaultData" value="0"/>
<setting name="SpiTransferStart" value="MSB"/>
<setting name="SpiByteSwapTransfer" value="false"/>
<setting name="SpiTimeClk2Cs" value="0.000001"/>
<setting name="SpiTimeCs2Clk" value="0.000001"/>
<setting name="SpiTimeCs2Cs" value="0.000001"/>
<array name="SpiTimeClk2Clk"/>
<setting name="SpiDeviceHalfDuplexSupport" value="false"/>
<setting name="SpiTransferWidth" value="TRANSFER_1_BIT"/>
<setting name="SpiHalfDuplexPinSelect" value="HALF_DUPLEX_SIN"/>
<setting name="SpiCsBehavior" value="CS_TOGGLE"/>
<setting name="SpiDeviceDmaRepeatedTransferSupport" value="false"/>
<array name="SpiDmaRepeatedTransferNotification"/>
<setting name="SpiHostRequest" value="DISABLE"/>
</struct>
</array>
<array name="SpiBaudrateConfig"/>
</struct>
<struct name="SpiGeneral">
<setting name="Name" value="SpiGeneral"/>
<setting name="SpiEnableUserModeSupport" value="false"/>
<setting name="SpiEnableDmaFastTransferSupport" value="false"/>
<setting name="SpiHalfDuplexModeSupport" value="false"/>
<setting name="LpspiIpDevErrorDetect" value="false"/>
<setting name="SpiGlobalDmaEnable" value="false"/>
<setting name="SpiEnableLargeFrameSize" value="false"/>
<setting name="SpiDmaRepeatedTransferEnable" value="false"/>
<setting name="SpiTimeoutMethod" value="OSIF_COUNTER_SYSTEM"/>
<setting name="SpiTransmitTimeout" value="1"/>
<array name="SpiPhyUnit">
<struct name="0">
<setting name="Name" value="SpiPhyUnit_0"/>
<setting name="SpiPhyUnitMapping" value="LPSPI_1"/>
<setting name="SpiPinConfiguration" value="0"/>
<setting name="SpiSamplePoint" value="0"/>
<setting name="SpiPhyUnitClockFunctionalGroupRef" value="ClockConfig0"/>
<setting name="SpiPhyUnitMode" value="SPI_MASTER"/>
<setting name="SpiPhyUnitAsyncUseDma" value="false"/>
<array name="SpiPhyTxDmaChannel"/>
<array name="SpiPhyRxDmaChannel"/>
<array name="SpiMaxDmaFastTransfer"/>
</struct>
</array>
</struct>
</config_set>
</instance>
<instance name="Siul2_Dio" uuid="646449b2-cd1b-42b8-966c-d47ce4ea8265" type="Siul2_Dio" type_id="Siul2_Dio" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="Siul2_Dio" quick_selection="Siul2DiotDefault">
<setting name="Name" value="Siul2_Dio"/>
<struct name="ConfigTimeSupport">
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
</struct>
<struct name="DioGeneral">
<setting name="Name" value="DioGeneral"/>
<setting name="SIUL2DioIPDevErrorDetect" value="true"/>
</struct>
</config_set>
</instance>
<instance name="Clock_Ip_ReferencePoints" uuid="ae2fffa4-c667-4a80-9e50-6096c14890c2" type="Clock_Ip_ReferencePoints" type_id="Clock_Ip_ReferencePoints" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="Clock_Ip_ReferencePoints">
<setting name="Name" value="Clock_Ip_ReferencePoints"/>
<struct name="ConfigTimeSupport">
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
</struct>
<array name="McuClockReferencePoint">
<struct name="0">
<setting name="Name" value="LPI2C1_CLK"/>
<setting name="McuClockFrequencySelect" value="AIPS_SLOW_CLK"/>
<setting name="Configuration" value="ClockConfig0"/>
</struct>
<struct name="1">
<setting name="Name" value="CORE_CLK"/>
<setting name="McuClockFrequencySelect" value="CORE_CLK"/>
<setting name="Configuration" value="ClockConfig0"/>
</struct>
</array>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="3b44895b-3e8c-432b-82e7-3c9b813209e0" type_id="system">
<config_set_global name="SystemModel" quick_selection="Default">
<setting name="Name" value="SystemModel"/>
<setting name="EcvdGenerationMethod" value="INDIVIDUAL"/>
<setting name="EcvdOutputPath" value=""/>
<setting name="EcvdGenerationTrigger" value="Generate Configuration"/>
<setting name="SyncFunctionalGroups" value="true"/>
<setting name="IgnoreComponentSuffix" value="true"/>
<setting name="ComponentGenerationMethod" value="EcucPostBuildVariants"/>
<setting name="DefaultFunctionalGroup" value="BOARD_InitPeripherals"/>
<struct name="PostBuildSelectable" quick_selection="Default">
<setting name="Name" value="PostBuildSelectable"/>
<array name="PredefinedVariants">
<struct name="0">
<setting name="Name" value="BOARD_InitPeripherals"/>
<setting name="Path" value="/system/SystemModel/PostBuildSelectable/BOARD_InitPeripherals"/>
<array name="PostBuildVariantCriterionValues"/>
</struct>
</array>
</struct>
<struct name="Criterions" quick_selection="Default">
<setting name="Name" value="Criterions"/>
<array name="PostBuildVariantCriterions"/>
</struct>
</config_set_global>
</component>
</components>
</periphs>
<serdes name="SERDES" version="1.0" enabled="false" update_project_code="true">
<generated_project_files/>
<components/>
</serdes>
</tools>
</configuration>