Added the 'one-instruction' latency on interrupts.

Author: ooPo

include/MOS6502/MOS6502.h

@@ -59,6 +59,7 @@ class MOS6502
   bool running = false;
 
   std::array<bool, INTERRUPT::COUNT> signals = {};
+  std::array<bool, INTERRUPT::COUNT> pending = {};
 
   WORD PC = { .w = 0x0000 };
   WORD AB = { .w = 0x0000 };
@@ -84,10 +85,20 @@ class MOS6502
     const int8_t offset = static_cast<int8_t>(Fetch());
 
     if (test) {
-      Idle();
       const uint16_t target = static_cast<uint16_t>(PC.w + offset);
-      if ((PC.w ^ target) & 0xFF00) { Load((PC.h << 8) | (target & 0xFF)); }
+      if ((PC.w ^ target) & 0xFF00) {
+        Idle();
+        PollInterrupts();
+        Load((PC.h << 8) | (target & 0xFF));
+      } else {
+        // Branch-taken quirk:
+        // A non-page-crossing taken branch suppresses the interrupt poll entirely.
+        // Any pending IRQ/NMI is therefore delayed by one additional instruction.
+        Idle();
+      }
       PC.w = target;
+    } else {
+      PollInterrupts();
     }
   }
 
@@ -127,9 +138,23 @@ class MOS6502
     Push(PC.h);
     Push(PC.l);
     Push(P.value | 0x20);
+
+    // NMI hijack
+    if (signals[INTERRUPT::NMI]) {
+      signals[INTERRUPT::NMI] = false;
+      pending[INTERRUPT::NMI] = false;
+      vector = 0xFFFA;
+    }
+
+    P.I  = 1;
     PC.l = Load(vector);
+    PollInterrupts();
     PC.h = Load(vector + 1);
-    P.I  = 1;
+  }
+
+  inline void PollInterrupts() {
+    if (signals[INTERRUPT::NMI]) { pending[INTERRUPT::NMI] = true; }
+    pending[INTERRUPT::IRQ] = !P.I && signals[INTERRUPT::IRQ];
   }
 
   [[nodiscard]] inline uint8_t Pull() {