After #160 is merged, we are missing the following.
Missing Instructions (0/14)
| ? |
Inst |
Ops |
Enc |
| ⬜ |
bvf |
vfpu-branch |
vfpu-branch |
| ⬜ |
bvfl |
vfpu-branch |
vfpu-branch |
| ⬜ |
bvt |
vfpu-branch |
vfpu-branch |
| ⬜ |
bvtl |
vfpu-branch |
vfpu-branch |
| ⬜ |
lvl.q |
vfpu-load16 |
vfpu-memory-quad |
| ⬜ |
lvr.q |
vfpu-load16 |
vfpu-memory-quad |
| ⬜ |
svl.q |
vfpu-store16 |
vfpu-memory-quad |
| ⬜ |
svr.q |
vfpu-store16 |
vfpu-memory-quad |
| ⬜ |
vcmovf |
vfpu-condmove |
vfpu-condmove |
| ⬜ |
vcmovt |
vfpu-condmove |
vfpu-condmove |
| ⬜ |
vcmp |
vfpu-compare |
vfpu-alu-compare |
| ⬜ |
vmfvc |
vfpu-control-read |
vfpu-read-control |
| ⬜ |
vmtvc |
vfpu-control-write |
vfpu-write-control |
| ⬜ |
vwbn |
vector-unary-mod |
vector-imm8 |
Do note that lvl.q / lvr.q corrupt registers and when implemented, we should probably add a mitigation to save/restore the affected COP1 register. Shouldn't be too difficult to do with the existing macro magic.
After #160 is merged, we are missing the following.
Missing Instructions (0/14)
Do note that lvl.q / lvr.q corrupt registers and when implemented, we should probably add a mitigation to save/restore the affected COP1 register. Shouldn't be too difficult to do with the existing macro magic.