USB-Core/Report.txt at main · pritam-sethuraman/USB-Core · GitHub

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Information: Updating design information... (UID-85)

****************************************
Report : design
Design : usb_phy_0
Version: H-2013.03-SP2
Date   : Thu Jun  1 20:27:40 2023
****************************************

Design allows ideal nets on clock nets.

Library(s) Used:

    class (File: /nfs/home/p/p_sethur/Synopsys/class.db)

Local Link Library:

    {class.db}

Flip-Flop Types:

    No flip-flop types specified.

Latch Types:

    No latch types specified.

Operating Conditions:

    No operating conditions specified.

Wire Loading Model:

    Selected automatically from the total cell area.

Name           :   10x10
Location       :   class
Resistance     :   0
Capacitance    :   1
Area           :   0
Slope          :   0.311
Fanout   Length   Points Average Cap Std Deviation
--------------------------------------------------------------
     1     0.53


Wire Loading Model Mode: top.

Timing Ranges:

    No timing ranges specified.

Pin Input Delays:

    None specified.

Pin Output Delays:

    None specified.

Disabled Timing Arcs:

    No arcs disabled.

Required Licenses:

    None Required

Design Parameters:

    usb_rst_det => 1'h0