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32 lines (29 loc) · 1.84 KB
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# Xpulp extension subset: post-incrementing load & store operations
# and register-register loads & store operations
# INFO: overlaps with rv_frep, rv_ssr, rv_dma
# Post-increment and reg-reg loads
p.lb.irpost rd rs1 imm12 14..12=0 6..2=0x02 1..0=3
p.lbu.irpost rd rs1 imm12 14..12=4 6..2=0x02 1..0=3
p.lh.irpost rd rs1 imm12 14..12=1 6..2=0x02 1..0=3
p.lhu.irpost rd rs1 imm12 14..12=5 6..2=0x02 1..0=3
p.lw.irpost rd rs1 imm12 14..12=2 6..2=0x02 1..0=3
p.lb.rrpost rd rs1 rs2 31..25=0x00 14..12=7 6..2=0x02 1..0=3
p.lbu.rrpost rd rs1 rs2 31..25=0x20 14..12=7 6..2=0x02 1..0=3
p.lh.rrpost rd rs1 rs2 31..25=0x08 14..12=7 6..2=0x02 1..0=3
p.lhu.rrpost rd rs1 rs2 31..25=0x28 14..12=7 6..2=0x02 1..0=3
p.lw.rrpost rd rs1 rs2 31..25=0x10 14..12=7 6..2=0x02 1..0=3
p.lb.rr rd rs1 rs2 31..25=0x00 14..12=7 6..2=0x00 1..0=3
p.lbu.rr rd rs1 rs2 31..25=0x20 14..12=7 6..2=0x00 1..0=3
p.lh.rr rd rs1 rs2 31..25=0x08 14..12=7 6..2=0x00 1..0=3
p.lhu.rr rd rs1 rs2 31..25=0x28 14..12=7 6..2=0x00 1..0=3
p.lw.rr rd rs1 rs2 31..25=0x10 14..12=7 6..2=0x00 1..0=3
# Post-increment and reg-reg stores
p.sb.irpost rs1 rs2 imm12hi imm12lo 14..12=0 6..2=0x0A 1..0=3
p.sh.irpost rs1 rs2 imm12hi imm12lo 14..12=1 6..2=0x0A 1..0=3
p.sw.irpost rs1 rs2 imm12hi imm12lo 14..12=2 6..2=0x0A 1..0=3
p.sb.rrpost rs1 rs2 prs3 31..25=0x00 14..12=4 6..2=0x0A 1..0=3
p.sh.rrpost rs1 rs2 prs3 31..25=0x00 14..12=5 6..2=0x0A 1..0=3
p.sw.rrpost rs1 rs2 prs3 31..25=0x00 14..12=6 6..2=0x0A 1..0=3
p.sb.rr rs1 rs2 prs3 31..25=0x00 14..12=4 6..2=0x08 1..0=3
p.sh.rr rs1 rs2 prs3 31..25=0x00 14..12=5 6..2=0x08 1..0=3
p.sw.rr rs1 rs2 prs3 31..25=0x00 14..12=6 6..2=0x08 1..0=3