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chihminchaocolluca
chihminchao
authored and
colluca
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ext-p : update table to v0.20 (riscv#413)
Quoted from spec "This version (020) differs from the previous one (019) with the addition of: * SHL instructions (shift left or right, logical) that are unsigned versions of the SHA instructions (shift left or right, arithmetic); and * for RV64 only, ‘P’-suffi x versions of PNCLIP instructions that are similar to RV32 PNCLIP instructions without shifting or rounding. The complete set of instructions added for RV32 are: PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS And for RV64: PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W" reference: https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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‎extensions/unratified/rv32_p‎

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@@ -10,6 +10,8 @@ $pseudo_op rv64_p::psslai.w sslai 31=1 30..28=0x5 27=0 26..25=0x
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# Page 7: Scalar Operand Shift Instructions - Pseudo-instructions
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$pseudo_op rv64_p::psshl.ws sshl 31=1 30..28=0x2 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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$pseudo_op rv64_p::psshlr.ws sshlr 31=1 30..28=0x3 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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$pseudo_op rv64_p::pssha.ws ssha 31=1 30..28=0x6 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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$pseudo_op rv64_p::psshar.ws sshar 31=1 30..28=0x7 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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@@ -272,6 +274,11 @@ padd.dhs 31=0 30..28=0x1 27=1 26..25=0x0 rs2 p_rs1_p 15..12=0x6 p_rd_
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padd.dws 31=0 30..28=0x1 27=1 26..25=0x1 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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padd.dbs 31=0 30..28=0x1 27=1 26..25=0x2 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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psshl.dhs 31=0 30..28=0x2 27=1 26..25=0x0 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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psshl.dws 31=0 30..28=0x2 27=1 26..25=0x1 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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psshlr.dhs 31=0 30..28=0x3 27=1 26..25=0x0 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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psshlr.dws 31=0 30..28=0x3 27=1 26..25=0x1 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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pssha.dhs 31=0 30..28=0x6 27=1 26..25=0x0 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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pssha.dws 31=0 30..28=0x6 27=1 26..25=0x1 rs2 p_rs1_p 15..12=0x6 p_rd_p 7..0=0x1b
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‎extensions/unratified/rv64_p‎

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@@ -18,10 +18,14 @@ pli.w 31=1 30..28=0x3 27=0 26..25=0x1 p_imm10 14..12=0x2 rd 6..
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psll.ws 31=1 30..28=0x0 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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padd.ws 31=1 30..28=0x1 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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psshl.ws 31=1 30..28=0x2 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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psshlr.ws 31=1 30..28=0x3 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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pssha.ws 31=1 30..28=0x6 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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sha 31=1 30..28=0x6 27=1 26..25=0x3 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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psshar.ws 31=1 30..28=0x7 27=1 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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shar 31=1 30..28=0x7 27=1 26..25=0x3 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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shl 31=1 30..28=0x2 27=1 26..25=0x3 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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shlr 31=1 30..28=0x3 27=1 26..25=0x3 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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# Page 6: Unary Instructions & PLUI (OP-IMM-32, funct3=010)
@@ -69,8 +73,17 @@ pmaccu.w.h01 31=1 30..27=0x7 26..25=0x1 rs2 rs1 14..12=0x1 rd 6..0=0x3b
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maccu.w01 31=1 30..27=0x7 26..25=0x3 rs2 rs1 14..12=0x1 rd 6..0=0x3b
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# Page 11: Shift-Add & ZIP/UNZIP Instructions (OP-32, funct3=010)
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pnclipup.b 31=1 30..28=0x0 27=0 26..25=0x0 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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pnclipup.h 31=1 30..28=0x0 27=0 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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pnclipup.w 31=1 30..28=0x0 27=0 26..25=0x3 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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psh1add.w 31=1 30..28=0x2 27=0 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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pssh1sadd.w 31=1 30..28=0x3 27=0 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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pnclipp.b 31=1 30..28=0x4 27=0 26..25=0x0 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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pnclipp.h 31=1 30..28=0x4 27=0 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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pnclipp.w 31=1 30..28=0x4 27=0 26..25=0x3 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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unzip8p 31=1 30..28=0x6 27=0 26..25=0x0 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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unzip16p 31=1 30..28=0x6 27=0 26..25=0x1 rs2 rs1 14..12=0x2 rd 6..0=0x3b
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unzip8hp 31=1 30..28=0x6 27=0 26..25=0x2 rs2 rs1 14..12=0x2 rd 6..0=0x3b

‎extensions/unratified/rv_p‎

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@@ -29,6 +29,8 @@ plui.h 31..27=0x1e 26..25=0x0 p_imm10 14..12=0x2 rd 6..0=0x1b
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# Page 7: Scalar Operand Shift/Add Instructions (OP-IMM-32, funct3=010)
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psll.hs 31=1 30..28=0x0 27=1 26..25=0x0 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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psll.bs 31=1 30..28=0x0 27=1 26..25=0x2 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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psshl.hs 31=1 30..28=0x2 27=1 26..25=0x0 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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psshlr.hs 31=1 30..28=0x3 27=1 26..25=0x0 rs2 rs1 14..12=0x2 rd 6..0=0x1b
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# Page 9: Packed Add/Sub Instructions (OP-32, funct3=000)
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padd.hs 31=1 30..28=0x1 27=1 26..25=0x0 rs2 rs1 14..12=0x2 rd 6..0=0x1b

‎src/riscv_opcodes/constants.py‎

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@@ -327,6 +327,8 @@ def read_arg_lut_csv(filename: str) -> "dict[str, tuple[int, int]]":
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"srari_rv32",
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"ssha",
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"sshar",
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"sshl",
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"sshlr",
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"sslai",
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"ssub",
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"ssubu",

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