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Add PULP extensions and LLVM tablegen generation - #22

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colluca merged 5 commits into
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Jul 21, 2026
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Add PULP extensions and LLVM tablegen generation#22
colluca merged 5 commits into
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snitch-new

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@colluca

@colluca colluca commented Jul 20, 2026

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  • Mirror the ISA extension organization for CSRs (Mirror ISA extension organization for CSRs riscv/riscv-opcodes#422, initial review received but not merged upstream). Enables generating LLVM tablegen descriptions for the custom CSRs.

  • Add --warn-overlap flag to CI tests.

  • Clean up PULP extensions

    • Replace Xpulppostmod with Xcvmem
    • Remove all FPalt format instructions, which have the exact same encoding as non-alternate-format instructions
    • Split SmallFloat ISA extension into per-precision subextensions
    • Remove draft bit-manipulation instructions from rv32_xb that were since ratified in rv_zbb, rv64_zbb, rv_zba, rv_zbc and rv_zbkb
    • Remove draft half-precision SmallFloat instructions from rv_xsmallfloat_h that were since ratified in rv_zfhmin, rv_zfh, rv64_zfh and rv_d_zfhmin
  • Add scripts to generate Tablegen inputs for custom LLVM 18 toolchains

  • Update scripts to generate Tablegen inputs for custom LLVM 22 toolchains (on top of the prior so LLVM 18 can be still supported by forking off the prior commit)

@colluca
colluca force-pushed the snitch-new branch 4 times, most recently from 93f1daa to 7a37944 Compare July 20, 2026 14:25
@colluca
colluca merged commit 81f691a into master Jul 21, 2026
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@colluca
colluca deleted the snitch-new branch July 21, 2026 10:23
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