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║ RAND ISMAAEL // COMPUTER ENGINEERING @ GT ║
║ embedded systems · computer architecture · C/C++ ║
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CE student at Georgia Tech (Systems & Architecture + Distributed Systems & Software Design) focused on the intersection of hardware and software. I like understanding how and why things work at the lowest level possible :)
Currently: undergraduate researcher at SIPLab + building a bare metal OS on an STM32 from scratch.
| project | stack | what it is |
|---|---|---|
| stm32-os | C · ARM Assembly | bare metal firmware w/ vector table, GPIO, SysTick, UART verified on hardware |
| chip8 | C++ · SDL2 | CHIP-8 emulator with full fetch-decode-execute cycle and function pointer opcode dispatch |
| RISC-V Pipeline | SystemVerilog | 5-stage RV32I pipelined processor with forwarding, hazard detection, stall control |
| Multithreaded UAV Simulation | C · OpenGL | 16-thread real-time simulation with PID control and collision response for 15 simultaneously active UAVs |
RISC-V Pipeline source unavailable (course IP)
SIPLab @ Georgia Tech: modeling 1P/2P photocurrent sensitivity across channelrhodopsin variants using finite-difference slope analysis and Hill function curve fitting. Currently refactoring the raster-scanning optogenetics module in CLEO, an open-source neural simulation library.
Fascinated by the "brains" that drive the world around us, whether in silicon or biology!
Languages: C · C++ · Python · SystemVerilog · ARM Assembly · RISC-V Assembly · VHDL
Hardware: STM32F103 · ARM Cortex-M3 · FPGA (Intel Quartus)
Tools: GDB · ST-Link · ModelSim · GTKWave · Git
Protocols: UART · SPI · I2C
- bare metal OS: GPIO → SysTick → UART → task switcher (in progress)
- undergraduate research at SIPLab on optogenetic neural simulation tooling
- seeking Fall 2026 / Spring 2027 embedded systems internships
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built from the ground up