GitHub - raphaeldickinson/Digital-Stopwatch-Cyclone-FPGA: Digital stopwatch implemented in Verilog for the Cyclone V FPGA (Quartus project).

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Digital-Stopwatch-Cyclone-FPGA

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Digital stopwatch implemented in Verilog for the Cyclone V FPGA (Quartus project).

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Name		Name	Last commit message	Last commit date
db		db
incremental_db		incremental_db
output_files		output_files
simulation/questa		simulation/questa
c5_pin_model_dump.txt		c5_pin_model_dump.txt
controlUnit.v		controlUnit.v
controlUnit.v.bak		controlUnit.v.bak
controlUnit_tb.v		controlUnit_tb.v
datapath.v		datapath.v
datapath.v.bak		datapath.v.bak
datapath_tb.v		datapath_tb.v
dffNegEdge.v		dffNegEdge.v
fullAdder.v		fullAdder.v
genericAdder.v		genericAdder.v
genericComparator.v		genericComparator.v
genericCounter.v		genericCounter.v
genericMux2x1.v		genericMux2x1.v
genericRegister.v		genericRegister.v
hexToSevenSeg.v		hexToSevenSeg.v
lab11.qpf		lab11.qpf
lab11.qsf		lab11.qsf
lab11.qws		lab11.qws
lab11_nativelink_simulation.rpt		lab11_nativelink_simulation.rpt
mod10counter.v		mod10counter.v
mod10counter_tb.v		mod10counter_tb.v
stopWatch_tb.v		stopWatch_tb.v
stopWatch_tb.v.bak		stopWatch_tb.v.bak
stopwatch.v		stopwatch.v
stopwatch.v.bak		stopwatch.v.bak

Digital stopwatch implemented in Verilog for the Cyclone V FPGA (Quartus project).

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