Confirmation about RVV instr src overlap check。

[Xu-Dsus4]

Hi all,
The RISC-V Vector Extension specification states:

A vector register cannot be used to provide source operands with more than one EEW for a single instruction. A mask register source is considered to have EEW=1 for this constraint. An encoding that would result in the same vector register being read with two or more different EEWs, including when the vector register appears at different positions within two or more vector register groups, is reserved.

My understanding is that, for .wv instructions such as vwadd.wv, Spike should check whether the source operands overlap in a way that causes the same vector register to be read with different EEWs. However, Spike does not appear to perform this check, resulting in a trap mismatch when executing the following instruction with LMUL=1:
vwadd.wv v8, v8, v9

riscv-isa-sim/riscv/v_ext_macros.h

Lines 181 to 191 in 262df8b

	#define VI_CHECK_DDS(is_rs) \
	VI_WIDE_CHECK_COMMON; \
	require_align(insn.rs2(), P.VU.vflmul * 2); \
	if (is_rs) { \
	require_align(insn.rs1(), P.VU.vflmul); \
	if (P.VU.vflmul < 1) { \
	require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
	} else { \
	require_noover_widen(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \
	} \
	}

Could you please confirm whether my interpretation is correct and whether this is a bug in Spike?

[aswaterman]

Your understanding of the spec is correct, but "reserved" does not mean "must raise an illegal-instruction exception". (Of course, raising an exception is a valid choice in this case, but it is not required.). So, Spike's behavior is one correct behavior among many.