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rvp for rv32/rv64 - #2246

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chihminchao:rvp-rv32-rv64
Apr 29, 2026
Merged

rvp for rv32/rv64#2246
aswaterman merged 10 commits into
riscv-software-src:masterfrom
chihminchao:rvp-rv32-rv64

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@chihminchao

@chihminchao chihminchao commented Mar 11, 2026

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The PR merges the works, #2210 and #2211 and the main author is @jason01180118. The changes from me are

  1. generate opcode from Refine rvp riscv/riscv-opcodes#409
  2. add disassembler
  3. fix some compilation warnings, names, and corner incorrect behavior

@chihminchao

chihminchao commented Mar 11, 2026

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For some reason, the CI was stuck as building step
https://github.com/riscv-software-src/riscv-isa-sim/actions/runs/22936376083/job/66568524696#step:4:3543746

arromanoff
arromanoff reviewed Mar 19, 2026
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Comment thread riscv/p_ext_macros.h Outdated
@chihminchao

chihminchao commented Mar 25, 2026

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Update : 03/26/2026

  1. add new instructions introduced by 0.20
  2. fix the compilation warning reported by @arromanoff
    all of them are caused by nclip-related ones in 9ed6e1c

@chihminchao

chihminchao commented Mar 25, 2026

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update: 03/26/2026

  1. forget to add rvp64 definition to makefile
  2. add missing macro for zip series
  3. make rv64p higher priority by overlap_list
  4. fix opcode typo for wsla ext-p: fix typo riscv/riscv-opcodes#414

aswaterman
aswaterman reviewed Mar 25, 2026
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Comment thread riscv/insns/psshar_dhs.h Outdated
aswaterman
aswaterman reviewed Mar 25, 2026
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Comment thread riscv/riscv.mk.in Outdated
aswaterman
aswaterman reviewed Mar 25, 2026
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Comment thread riscv/decode.h Outdated
aswaterman
aswaterman reviewed Mar 25, 2026
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Comment thread riscv/insns/pabdu_b.h Outdated
aswaterman
aswaterman reviewed Mar 25, 2026
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Comment thread riscv/insns/pabd_b.h Outdated
@chihminchao

chihminchao commented Apr 8, 2026

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Several change in this version

  1. use a new macro to tell clip and sati. The saturation behavior is a little different
  2. return the even register number rather than encoding field
  3. mimic V/Q to check int128 support and use standard in128_t type
  4. simplify abd related calculation
  5. add missing vxsat update for some saturation instructions.

aswaterman
aswaterman reviewed Apr 8, 2026
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Comment thread riscv/insn_template.h
@aswaterman

aswaterman commented Apr 15, 2026

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@chihminchao you might want to flatten the PR to a single commit to speed up CI iteration time, since the CI runs on every single commit. (In fact, it might be timing out because of the number of commits. I didn't check.)

@chihminchao

chihminchao commented Apr 16, 2026

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@chihminchao you might want to flatten the PR to a single commit to speed up CI iteration time, since the CI runs on every single commit. (In fact, it might be timing out because of the number of commits. I didn't check.)

Ok, I will rebase and merge some of them to reduce CI running time. I am not aware that CI tries to build commit-by-commit. So rigorous.

@aswaterman

aswaterman commented Apr 16, 2026

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Yeah, the intent is to make git bisect consistently work, which it doesn't if some intermediate commits are broken.

@chihminchao

chihminchao commented Apr 17, 2026

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Update at 04/17/2026

  1. rebase and merge commits to reduce number of commits to satisfy CI execution time budget

@chihminchao

chihminchao commented Apr 20, 2026

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Update : 2026/04/20
merge and split some patches to make each commit error-free

jason01180118 and others added 4 commits April 19, 2026 22:32
@jason01180118 @chihminchao
rvp: disasm: add simd and register-pair instruction support
028a698
@chihminchao
rvp: add opcode
5b910fd 
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@jason01180118 @chihminchao
rvp: add packed instructions for rv32 - part1
e4ad451 
  add the following categories

  * packed add/sub/pli instructions
  * packed cross instructions
  * packed absolute instructions
  * packed accumulation instructions
  * packed sign-extend and saturating instructions
  * packed shift instructions
  * packed compare instructions
  * packed pack instructions
  * packed basic arithmetic and data-move
  * packed multiply instructions
  * packed accumulate instructions
  * packed multiply-add instructions
  * RD-only element-wise register-pair
@jason01180118 @chihminchao
rvp: add packed instructions for rv32 - part2
2e2748b 
 Add the following instructions to rv32

 * packed add/sub register-pair instructions
 * packed cross register-pair instructions
 * packed absolute register-pair instructions
 * packed accumulation register-pair instructions
 * packed sign-extend and saturating
 * packed shift register-pair instructions
 * packed compare register-pair instructions
 * packed pack register-pair instructions
 * packed zip register-pair instructions
 * packed narrowing shift and clip register-pair
 * packed multiply register-pair instructions
 * packed accumulate register-pair instructions
 * packed multiply-add register-pair instructions
@jason01180118 @chihminchao
rvp: add packed instructions for rv64 - part1
71b7473 
  Add the following categories

  * RD-only element-wise instructions (_w suffix
  * packed add/sub instructions (_w suffix only)
  * packed cross instructions (_wx suffix only)
  * packed accumulation instructions (_ws suffix
  * packed sign-extend and saturating instructions
  * packed shift instructions (_w/_ws suffix and
  * packed compare instructions (_w suffix only)
  * packed pack instructions (_h/_w suffix only)
  * rev_rv32/rev/rev16
jason01180118 and others added 4 commits April 20, 2026 00:30
@jason01180118 @chihminchao
rvp: add packed instructions for rv64 - part2
d4a87e9 
  Add the following categories

  * packed zip and unzip instructions
  * packed basic arithmetic and data-move
  * packed multiply instructions (_w suffix only)
  * packed accumulate instructions (_w suffix
  * packed multiply-add instructions (_w/_h suffix
  * packed sati/usati/srari for rv64

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvp: new instructions from 0.20
7a42a63 
The complete set of instructions added for RV32 are:
  PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS
  PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS
And for RV64:
  PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W
  PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W

reference:
  https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf
https://www.jhauser.us/RISCV/ext-P/RVP-baseInstrs-Sail-020.txt

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvp: add disassembler
9983d20 
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvp: add missing vxsat CSR writes for 70 saturating instructions
91a0deb 
Per the P-extension spec, any instruction that performs saturation must
set the vxsat CSR to 1 when the result is clamped. 70 instructions were
missing this write, addressed here in two ways:

1. Convert P_SAT, P_USAT, and P_USAT_FULL macros from pure expression
   macros to GCC statement expressions that detect when saturation
   occurs and write P.VU.vxsat. This automatically fixes ~42
   instructions that use these macros (nclip/nclipi/nclipr/nclipri
   families, psati, psslai, pssh1sadd, pusati, sati, usati, ssh1sadd,
   sslai, and their packed/double-wide variants).

2. Add explicit vxsat writes to 22 instructions with inline saturation
   logic that bypasses the macros:
   - mulq/mulqr/pmulq/pmulqr: set vxsat on INT_MIN * INT_MIN overflow
   - psas/pssa cross variants: set vxsat from sat_add/sat_sub sat flag
   - pssha/psshar DW variants: set vxsat from ov overflow flag
   - pssha/psshar/ssha/sshar: set vxsat in sshamt >= BIT overflow path
   - pusati_dh/pusati_dw: set vxsat on unsigned range clamping

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao

chihminchao commented Apr 20, 2026

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@aswaterman Finally, it passes CI and also needs riscv/riscv-opcodes#414 for opcode fix

@chihminchao
rvp: replace __int128 with int128_t/uint128_t and guard p-ext by HAVE…
f2aa295 
…_INT128

Replace bare __int128 / unsigned __int128 in psshar_dhs.h and psshar_dws.h
with the int128_t / uint128_t typedefs from fesvr/byteorder.h, and guard
the entire riscv_insn_ext_p list in riscv.mk.in with $(if $(HAVE_INT128),...)
matching the existing pattern for the V extension

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao

chihminchao commented Apr 29, 2026

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update: 2026/04/29

  1. handle -Wshift-negative-value issue
    The behavior is undefined before c++20. Though we set c++2a as default standard, gcc 11 still triggers this when -Wextra is specified.

@aswaterman
aswaterman merged commit b21cccd into riscv-software-src:master Apr 29, 2026
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@chihminchao chihminchao mentioned this pull request Apr 30, 2026
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@chihminchao @aswaterman @arromanoff @jason01180118