Extended Olympia to support vector load and store instructions.
Extend the current LSU so that it can "unroll" a vector instruction and generate separate memory accesses for each active vector element. For simplicity, read and write ports to the VRF (vector register file) can be added to the LSU for writing load data and reading store data, the vector mask register and the index values (for indexed loads and stores).
The design should include the following components:
- An "address unroller" for generating load/store requests from a vector instruction.
- A buffer for holding load data before writing the data into the VRF
Resources:
The RISC-V Vector ISA Tutorial (good intro, but it's for RVV 0.7 so beware!)
RISC-V Vector in a Nutshell
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor (inspiration?)
Extended Olympia to support vector load and store instructions.
Extend the current LSU so that it can "unroll" a vector instruction and generate separate memory accesses for each active vector element. For simplicity, read and write ports to the VRF (vector register file) can be added to the LSU for writing load data and reading store data, the vector mask register and the index values (for indexed loads and stores).
The design should include the following components:
Resources:
The RISC-V Vector ISA Tutorial (good intro, but it's for RVV 0.7 so beware!)
RISC-V Vector in a Nutshell
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor (inspiration?)