Commit 4d172ae
Submodule riscv-tests updated 22 files
- .github/workflows/spike-tests.yml+124
- benchmarks/common/util.h+18-15
- benchmarks/mm/mm_main.c+4-1
- benchmarks/mt-matmul/mt-matmul.c+3-1
- benchmarks/mt-memcpy/mt-memcpy.c+7-6
- benchmarks/mt-vvadd/mt-vvadd.c+8-6
- benchmarks/vec-daxpy/vec-daxpy.S+15-14
- benchmarks/vec-daxpy/vec-daxpy_main.c+3-3
- benchmarks/vec-sgemm/vec-sgemm.S+15-7
- isa/Makefile+8-2
- isa/hypervisor-svadu/2-stage_translation_implicit_store_error.S+131
- isa/hypervisor-svadu/2-stage_translation_implicit_store_error_hs.S+138
- isa/hypervisor-svadu/Makefrag+9
- isa/hypervisor/2-stage_translation_implicit_load_error.S+121
- isa/hypervisor/2-stage_translation_implicit_load_error_hs.S+129
- isa/hypervisor/Makefrag+2
- isa/rv32uzicond/Makefrag+10
- isa/rv32uzicond/czero_eqz.S+7
- isa/rv32uzicond/czero_nez.S+7
- isa/rv64uzicond/Makefrag+10
- isa/rv64uzicond/czero_eqz.S+76
- isa/rv64uzicond/czero_nez.S+76
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