Add xCAUSE interrupt and exception code field masks (#427)

* Add MCAUSE/SCAUSE/UCAUSE Interrupt and Exception Code field masks

Define MCAUSE32/64_INT and MCAUSE32/64_EXCCODE for the Interrupt and
Exception Code fields of mcause, plus XLEN-generic aliases in the
__riscv_xlen selection block, following the same pattern used for
MSTATUS_SD and SATP_MODE. scause and ucause share the identical bit
layout per the privileged spec, so SCAUSE_* and UCAUSE_* are defined
as aliases of the MCAUSE_* masks.

* Remove UCAUSE macros

There is no ucause CSR in the privileged spec, so the UCAUSE32/64_INT
and UCAUSE32/64_EXCCODE masks (and the UCAUSE_INT/UCAUSE_EXCCODE
xlen-generic aliases) don't apply.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

---------

Co-authored-by: Claude Sonnet 5 <noreply@anthropic.com>

Author: colluca

encoding.h

@@ -171,6 +171,16 @@
 
 #define MIDELEG_FORCED_MASK MIP_HS_MASK
 
+#define MCAUSE32_INT     _RISCV_UL(0x80000000)
+#define MCAUSE32_EXCCODE _RISCV_UL(0x7FFFFFFF)
+#define MCAUSE64_INT     _RISCV_ULL(0x8000000000000000)
+#define MCAUSE64_EXCCODE _RISCV_ULL(0x7FFFFFFFFFFFFFFF)
+
+#define SCAUSE32_INT     MCAUSE32_INT
+#define SCAUSE32_EXCCODE MCAUSE32_EXCCODE
+#define SCAUSE64_INT     MCAUSE64_INT
+#define SCAUSE64_EXCCODE MCAUSE64_EXCCODE
+
 #define SIP_SSIP MIP_SSIP
 #define SIP_STIP MIP_STIP
 
@@ -521,11 +531,19 @@
 # define SSTATUS_SD SSTATUS64_SD
 # define RISCV_PGLEVEL_BITS 9
 # define SATP_MODE SATP64_MODE
+# define MCAUSE_INT MCAUSE64_INT
+# define MCAUSE_EXCCODE MCAUSE64_EXCCODE
+# define SCAUSE_INT SCAUSE64_INT
+# define SCAUSE_EXCCODE SCAUSE64_EXCCODE
 #else
 # define MSTATUS_SD MSTATUS32_SD
 # define SSTATUS_SD SSTATUS32_SD
 # define RISCV_PGLEVEL_BITS 10
 # define SATP_MODE SATP32_MODE
+# define MCAUSE_INT MCAUSE32_INT
+# define MCAUSE_EXCCODE MCAUSE32_EXCCODE
+# define SCAUSE_INT SCAUSE32_INT
+# define SCAUSE_EXCCODE SCAUSE32_EXCCODE
 #endif
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)