Merge pull request #22 from pulp-platform/snitch-new

Add PULP extensions and LLVM tablegen generation

Author: colluca

.github/workflows/python-app.yml

@@ -46,7 +46,7 @@ jobs:
     # Generate all output with code coverage. Unfortunately due to limitations in
     # the `coverage` tool we need to run `riscv_opcodes` as a module.
     - name: Generate
-      run: uv run -- coverage run -m riscv_opcodes -c -chisel -sverilog -rust -latex -spinalhdl -svg -go "rv*" "unratified/rv*"
+      run: uv run -- coverage run -m riscv_opcodes --warn-overlap -c -chisel -sverilog -rust -latex -spinalhdl -svg -go "rv*" "unratified/rv*"
 
     - name: Check C output
       run: cat encoding.out.h | cpp

.gitignore

@@ -10,6 +10,9 @@ inst.spinalhdl
 inst.sverilog
 inst.svg
 instr_dict.json
+inst.*.td
+csr.td
+feature.td
 
 __pycache__/
 

Makefile

@@ -5,6 +5,7 @@ ENV_H := ../riscv-tests/env/encoding.h
 OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h
 INSTALL_HEADER_FILES := $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H)
 PSEUDO_FLAG := $(if $(PSEUDO),-pseudo,)
+FLAGS := --warn-overlap
 
 ifeq ($(shell command -v uv 2>/dev/null),)
 	RUNNER := PYTHONPATH=src python -m
@@ -21,25 +22,25 @@ pseudo:
 	@$(MAKE) PSEUDO=1 everything
 
 everything:
-	@$(RUNNER) riscv_opcodes $(PSEUDO_FLAG) -c -go -chisel -sverilog -rust -latex -spinalhdl $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) $(PSEUDO_FLAG) -c -go -chisel -sverilog -rust -latex -spinalhdl $(EXTENSIONS)
 
 encoding.out.h:
-	@$(RUNNER) riscv_opcodes -c $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -c $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.chisel:
-	@$(RUNNER) riscv_opcodes -chisel $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -chisel $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.go:
-	@$(RUNNER) riscv_opcodes -go $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -go $(PSEUDO_FLAG) $(EXTENSIONS)
 
 latex:
-	@$(RUNNER) riscv_opcodes -latex $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -latex $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.sverilog:
-	@$(RUNNER) riscv_opcodes -sverilog $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -sverilog $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.rs:
-	@$(RUNNER) riscv_opcodes -rust $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -rust $(PSEUDO_FLAG) $(EXTENSIONS)
 
 clean:
 	rm -f inst* priv-instr-table.tex encoding.out.h
@@ -58,4 +59,4 @@ instr-table.tex: latex
 priv-instr-table.tex: latex
 
 inst.spinalhdl:
-	@$(RUNNER) riscv_opcodes -spinalhdl $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -spinalhdl $(PSEUDO_FLAG) $(EXTENSIONS)

PULP.md

@@ -0,0 +1,6 @@
+# Adding a custom ISA extension
+
+If you have a custom ISA extension, create a new file under `extensions/unratified`.
+The extension name should be prefixed with an `x` to properly identify custom extensions; refer to the existing extensions.
+
+Finally, list the extension in `pulp-extensions.txt` for it to be picked up as a PULP extension, e.g. by our compiler generation scripts.

arg_lut.csv

@@ -113,3 +113,10 @@
 "p_rd_p", 11, 8
 "p_rs1_p", 19, 16
 "p_rs2_p", 24, 21
+"shamt", 25, 20
+"prs3", 11, 7
+"L", 7, 7
+"uimms", 19, 15
+"Luimm5", 29, 25
+"stagger_max", 14, 12
+"stagger_mask", 11, 8

csrs.csv csrs/csrs.csvcsrs.csv renamed to csrs/csrs.csv

@@ -0,0 +1,15 @@
+# PULP/Snitch custom CSRs.
+#
+# format of a line in this file:
+# 0xENCODING, "csr_name"
+0x7C0, "ssr"
+0x7C3, "sc"
+0x7C4, "user_low"
+0x7C5, "user_high"
+# Smallfloat and misc PULP CSRs
+0x7C1, "fpmode"
+0x7C2, "barrier"
+0x7C6, "copift"
+0x7C7, "dump"
+0x7D1, "stacklimit"
+0x800, "fmode"

csrs32.csv csrs/csrs32.csvcsrs32.csv renamed to csrs/csrs32.csv

@@ -486,6 +486,28 @@
 #define IRQ_RAS_LOW_PRIO  35
 #define IRQ_RAS_HIGH_PRIO 43
 
+/* PULP/Snitch custom interrupt sources */
+#define IRQ_HOST          13  /* legacy alias for IRQ_LCOF */
+#define IRQ_S_CLUSTER     17
+#define IRQ_M_CLUSTER     19
+#define IRQ_M_ACC         20  /* machine-level accelerator interrupt */
+
+#define MIP_SCIP          (1 << IRQ_S_CLUSTER)
+#define MIP_MCIP          (1 << IRQ_M_CLUSTER)
+#define MIP_MXIP          (1 << IRQ_M_ACC)
+
+/* PULP/Snitch custom CSR addresses */
+#define CSR_SSR           0x7C0  // Stream semantic registers
+#define CSR_FPMODE        0x7C1  // Floating-point mode
+#define CSR_BARRIER       0x7C2  // Hardware barrier
+#define CSR_SC            0x7C3  // Scalar chaining
+#define CSR_USER_LOW      0x7C4  // AWUSER[31:0]
+#define CSR_USER_HIGH     0x7C5  // AWUSER[63:32]
+#define CSR_COPIFT        0x7C6  // Enable COPIFT
+#define CSR_DUMP          0x7C7  // Dump CSR
+#define CSR_STACKLIMIT    0x7D1  // Mempool stack overflow limit
+#define CSR_FMODE         0x800  // Floating-point mode (legacy)
+
 /* page table entry (PTE) fields */
 #define PTE_V     0x001 /* Valid */
 #define PTE_R     0x002 /* Read */