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Added some V extension Pseudo-instructions #295

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Added some V extension Pseudo-instructions #295

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c7c6877
Added some V extension Pseudo-instructions
Oct 7, 2024
766c468
Fixed wrong pseudo instruction definition
Oct 25, 2024
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22 changes: 22 additions & 0 deletions rv_v
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Original file line number Diff line number Diff line change
Expand Up @@ -209,6 +209,12 @@ vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57
vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57
vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57

#Pseudo OPFVV

$pseudo_op rv_v::vfsgnjn.vv vfneg.v 31..26=0x09 vm vs2=vs1 vs1 14..12=0x1 vd 6..0=0x57
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$pseudo_op rv_v::vmflt.vv vmfgt.vv 31..26=0x1b vm vs1 vs2 14..12=0x5 vd 6..0=0x57
$pseudo_op rv_v::vmfle.vv vmfge.vv 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57

# OPIVX
vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
Expand Down Expand Up @@ -302,6 +308,13 @@ vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57
vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57

#Pseudo OPIVV

$pseudo_op rv_v::vmslt.vv vmsgt.vv 31..26=0x1b vm vs1 vs2 14..12=0x0 vd 6..0=0x57
$pseudo_op rv_v::vmsltu.vv vmsgtu.vv 31..26=0x1a vm vs1 vs2 14..12=0x0 vd 6..0=0x57
$pseudo_op rv_v::vmsle.vv vmsge.vv 31..26=0x1d vm vs1 vs2 14..12=0x0 vd 6..0=0x57
$pseudo_op rv_v::vmsleu.vv vmsgeu.vv 31..26=0x1c vm vs1 vs2 14..12=0x0 vd 6..0=0x57

@aswaterman Andrew Waterman (aswaterman) Oct 7, 2024

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Same concern as for the FP comparisons.


# OPIVI
vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
Expand Down Expand Up @@ -411,6 +424,13 @@ vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57
vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57

#Pseudo-Instructions for Vector Integer Extension Instructions

$pseudo_op rv_v::vmxor.mm vmclr.m 31..26=0x1b 25=1 vs2=vd vs1=vd 14..12=0x2 vd 6..0=0x57

@aswaterman Andrew Waterman (aswaterman) Oct 7, 2024 •
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More of a question than a comment: is there a reason for using vs2=vd rather than vs2=vs1 here? By transitivity, they're equivalent; I'm just curious if there should be a stylistic default and, if so, why.

@AFOliveira Afonso Oliveira (AFOliveira) Oct 8, 2024

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This is to ensure that the parsing assumes them as the same value. This is extremely useful when generating, per example, the yaml_dump since we can know what differs from the original instruction to the pseudo-instruction.

This can be parsed to ouput, per example, the following: https://github.com/riscv-software-src/riscv-unified-db/blob/00213d2b2703240dc4fbe90dcdd8749e5b5f7e35/arch/inst/B/add.uw.yaml#L25

@aswaterman Andrew Waterman (aswaterman) Oct 8, 2024

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I think you missed my point. There are two equivalent ways of expressing this: we can say vs2=vd and vs1=vd, or we can say vs1=vd and vs2=vs1. The same information would be conveyed to parsing tools either way. I am just wondering why we are anchoring on vd.

@AFOliveira Afonso Oliveira (AFOliveira) Oct 14, 2024

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I definitely missed it, but I believe the best way to go for it is to say that "original_field = other_field", since parsing wise this is more helpful

$pseudo_op rv_v::vmnand.mm vmnot.m 31..26=0x1d 25=1 vs2=vs1 vs1 14..12=0x2 vd 6..0=0x57
$pseudo_op rv_v::vmand.mm vmmv.m 31..26=0x19 25=1 vs2=vs1 vs1 14..12=0x2 vd 6..0=0x57
$pseudo_op rv_v::vmxnor.mm vmset.m 31..26=0x1f 25=1 vs2=vd vs1=vd 14..12=0x2 vd 6..0=0x57
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# OPMVX
vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
Expand Down Expand Up @@ -449,3 +469,5 @@ vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57
vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57
vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57
vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57

$pseudo_op rv_v::vfsgnjx.vv vfabs.v 31..26=0x0a vm vs2=vs1 vs1 14..12=0x1 vd 6..0=0x57
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