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Change immediate type of select vector-immediate instructions to zimm5 - #393

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Andrew Waterman (aswaterman) merged 1 commit into
riscv:masterfrom
robinali-codasip:user/robin.ali/rvv_zimm5
Dec 4, 2025
Merged

Change immediate type of select vector-immediate instructions to zimm5#393
Andrew Waterman (aswaterman) merged 1 commit into
riscv:masterfrom
robinali-codasip:user/robin.ali/rvv_zimm5

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@robinali-codasip

@robinali-codasip robinali-codasip commented Dec 3, 2025

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According to the RISC-V unprivileged spec, the following instructions have a zero-extended immediate:

1.     vsll.vi
2.     vsrl.vi
3.     vsra.vi
4.     vnsrl.wi
5.     vnsra.wi
6.     vssrl.vi
7.     vssra.vi
8.     vnclipu.wi
9.     vnclip.wi
10.     vslideup.vi
11.     vslidedown.vi
12.     vrgather.vi

According to the RISC-V unprivileged spec, the following instructions
have a zero-extended immediate:
* vsll_vi
* vsrl_vi",
* vsra_vi
* vnsrl_wi
* vnsra_wi
* vssrl_vi
* vssra_vi
* vnclipu_wi
* vnclip_wi
* vslideup_vi
* vslidedown_vi
* vrgather_vi
@codecov

codecov Bot commented Dec 3, 2025

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Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 97.08%. Comparing base (383cbca) to head (ea70517).
⚠️ Report is 46 commits behind head on master.

Additional details and impacted files
@@            Coverage Diff             @@
##           master     #393      +/-   ##
==========================================
+ Coverage   96.53%   97.08%   +0.55%     
==========================================
  Files          10       14       +4     
  Lines         750      926     +176     
==========================================
+ Hits          724      899     +175     
- Misses         26       27       +1     

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@robinali-codasip

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Related issue: #394

@aswaterman

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Thanks for the improvement.

@aswaterman
Andrew Waterman (aswaterman) merged commit 72b2926 into riscv:master Dec 4, 2025
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2 participants