Legacy branch

.github/workflows/python-app.yml

@@ -46,7 +46,7 @@ jobs:
     # Generate all output with code coverage. Unfortunately due to limitations in
     # the `coverage` tool we need to run `riscv_opcodes` as a module.
     - name: Generate
-      run: uv run -- coverage run -m riscv_opcodes -c -chisel -sverilog -rust -latex -spinalhdl -svg -go "rv*" "unratified/rv*"
+      run: uv run -- coverage run -m riscv_opcodes --warn-overlap -c -chisel -sverilog -rust -latex -spinalhdl -svg -go "rv*" "unratified/rv*"
 
     - name: Check C output
       run: cat encoding.out.h | cpp

.gitignore

@@ -10,6 +10,9 @@ inst.spinalhdl
 inst.sverilog
 inst.svg
 instr_dict.json
+inst.*.td
+csr.td
+feature.td
 
 __pycache__/
 

Makefile

@@ -5,6 +5,7 @@ ENV_H := ../riscv-tests/env/encoding.h
 OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h
 INSTALL_HEADER_FILES := $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H)
 PSEUDO_FLAG := $(if $(PSEUDO),-pseudo,)
+FLAGS := --warn-overlap
 
 ifeq ($(shell command -v uv 2>/dev/null),)
 	RUNNER := PYTHONPATH=src python -m
@@ -21,25 +22,25 @@ pseudo:
 	@$(MAKE) PSEUDO=1 everything
 
 everything:
-	@$(RUNNER) riscv_opcodes $(PSEUDO_FLAG) -c -go -chisel -sverilog -rust -latex -spinalhdl $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) $(PSEUDO_FLAG) -c -go -chisel -sverilog -rust -latex -spinalhdl $(EXTENSIONS)
 
 encoding.out.h:
-	@$(RUNNER) riscv_opcodes -c $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -c $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.chisel:
-	@$(RUNNER) riscv_opcodes -chisel $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -chisel $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.go:
-	@$(RUNNER) riscv_opcodes -go $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -go $(PSEUDO_FLAG) $(EXTENSIONS)
 
 latex:
-	@$(RUNNER) riscv_opcodes -latex $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -latex $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.sverilog:
-	@$(RUNNER) riscv_opcodes -sverilog $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -sverilog $(PSEUDO_FLAG) $(EXTENSIONS)
 
 inst.rs:
-	@$(RUNNER) riscv_opcodes -rust $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -rust $(PSEUDO_FLAG) $(EXTENSIONS)
 
 clean:
 	rm -f inst* priv-instr-table.tex encoding.out.h
@@ -58,4 +59,4 @@ instr-table.tex: latex
 priv-instr-table.tex: latex
 
 inst.spinalhdl:
-	@$(RUNNER) riscv_opcodes -spinalhdl $(PSEUDO_FLAG) $(EXTENSIONS)
+	@$(RUNNER) riscv_opcodes $(FLAGS) -spinalhdl $(PSEUDO_FLAG) $(EXTENSIONS)

PULP.md

@@ -0,0 +1,6 @@
+# Adding a custom ISA extension
+
+If you have a custom ISA extension, create a new file under `extensions/unratified`.
+The extension name should be prefixed with an `x` to properly identify custom extensions; refer to the existing extensions.
+
+Finally, list the extension in `pulp-extensions.txt` for it to be picked up as a PULP extension, e.g. by our compiler generation scripts.

arg_lut.csv

@@ -113,3 +113,10 @@
 "p_rd_p", 11, 8
 "p_rs1_p", 19, 16
 "p_rs2_p", 24, 21
+"shamt", 25, 20
+"prs3", 11, 7
+"L", 7, 7
+"uimms", 19, 15
+"Luimm5", 29, 25
+"stagger_max", 14, 12
+"stagger_mask", 11, 8

csrs/unratified/rv_xpulp.csv

@@ -0,0 +1,15 @@
+# PULP/Snitch custom CSRs.
+#
+# format of a line in this file:
+# 0xENCODING, "csr_name"
+0x7C0, "ssr"
+0x7C3, "sc"
+0x7C4, "user_low"
+0x7C5, "user_high"
+# Smallfloat and misc PULP CSRs
+0x7C1, "fpmode"
+0x7C2, "barrier"
+0x7C6, "copift"
+0x7C7, "dump"
+0x7D1, "stacklimit"
+0x800, "fmode"

encoding.h

@@ -486,6 +486,28 @@
 #define IRQ_RAS_LOW_PRIO  35
 #define IRQ_RAS_HIGH_PRIO 43
 
+/* PULP/Snitch custom interrupt sources */
+#define IRQ_HOST          13  /* legacy alias for IRQ_LCOF */
+#define IRQ_S_CLUSTER     17
+#define IRQ_M_CLUSTER     19
+#define IRQ_M_ACC         20  /* machine-level accelerator interrupt */
+
+#define MIP_SCIP          (1 << IRQ_S_CLUSTER)
+#define MIP_MCIP          (1 << IRQ_M_CLUSTER)
+#define MIP_MXIP          (1 << IRQ_M_ACC)
+
+/* PULP/Snitch custom CSR addresses */
+#define CSR_SSR           0x7C0  // Stream semantic registers
+#define CSR_FPMODE        0x7C1  // Floating-point mode
+#define CSR_BARRIER       0x7C2  // Hardware barrier
+#define CSR_SC            0x7C3  // Scalar chaining
+#define CSR_USER_LOW      0x7C4  // AWUSER[31:0]
+#define CSR_USER_HIGH     0x7C5  // AWUSER[63:32]
+#define CSR_COPIFT        0x7C6  // Enable COPIFT
+#define CSR_DUMP          0x7C7  // Dump CSR
+#define CSR_STACKLIMIT    0x7D1  // Mempool stack overflow limit
+#define CSR_FMODE         0x800  // Floating-point mode (legacy)
+
 /* page table entry (PTE) fields */
 #define PTE_V     0x001 /* Valid */
 #define PTE_R     0x002 /* Read */

extensions/unratified/rv32_xb

@@ -0,0 +1,90 @@
+# RV32B: bit manipulation
+
+# INFO: overlaps with rv32_xpulpminmax, rv32_xpulpbitop, rv32_xpulpbitopsmall
+
+# Since the original draft proposal, the following have now been ratified
+# in rv_zbb.
+# With the same encoding
+#   andn       rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3
+#   orn        rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3
+#   xnor       rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3
+#   clz        rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3
+#   ctz        rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3
+#   sext.b     rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3
+#   sext.h     rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3
+#   rol        rd rs1 rs2 31..25=48 14..12=1 6..2=0x0C 1..0=3
+#   ror        rd rs1 rs2 31..25=48 14..12=5 6..2=0x0C 1..0=3
+#   min        rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3
+#   maxu       rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3
+# With swapped encoding
+#   max        rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3
+#   minu       rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3
+# Same encoding but changed name (pcnt -> cpop)
+#   pcnt       rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3
+
+# Since the original draft proposal, the following have now been ratified
+# in rv64_zbb, with almost the same encoding (shamt -> shamtd)
+#   rori       rd rs1 31..26=24 shamt 14..12=5 6..2=0x04 1..0=3
+
+# Since the original draft proposal, the following have now been ratified
+# in rv_zba, with the same encoding.
+#   sh1add     rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3
+#   sh2add     rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3
+#   sh3add     rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3
+
+# Since the original draft proposal, the following have now been ratified
+# in rv_zbc, with the same encoding.
+#   clmul      rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3
+#   clmulr     rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3
+#   clmulh     rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3
+
+# Since the original draft proposal, the following have now been ratified
+# in rv_zbkb, with the same encoding.
+#   pack       rd rs1 rs2 31..25=4  14..12=4 6..2=0x0C 1..0=3
+#   packh      rd rs1 rs2 31..25=4  14..12=7 6..2=0x0C 1..0=3
+
+
+slo        rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3
+sro        rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3
+
+sbclr      rd rs1 rs2 31..25=36 14..12=1 6..2=0x0C 1..0=3
+sbset      rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3
+sbinv      rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3
+sbext      rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3
+gorc       rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3
+grev       rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3
+
+sloi       rd rs1 31..26=8  shamt 14..12=1 6..2=0x04 1..0=3
+sroi       rd rs1 31..26=8  shamt 14..12=5 6..2=0x04 1..0=3
+
+sbclri     rd rs1 31..26=18 shamt 14..12=1 6..2=0x04 1..0=3
+sbseti     rd rs1 31..26=10 shamt 14..12=1 6..2=0x04 1..0=3
+sbinvi     rd rs1 31..26=26 shamt 14..12=1 6..2=0x04 1..0=3
+sbexti     rd rs1 31..26=18 shamt 14..12=5 6..2=0x04 1..0=3
+gorci      rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3
+grevi      rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3
+
+cmix       rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3
+cmov       rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3
+
+fsl        rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3
+fsr        rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3
+fsri       rd rs1 shamt rs3   26=1 14..12=5 6..2=0x04 1..0=3
+
+crc32.b    rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3
+crc32.h    rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3
+crc32.w    rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3
+crc32c.b   rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3
+crc32c.h   rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3
+crc32c.w   rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3
+
+shfl       rd rs1 rs2 31..25=4  14..12=1 6..2=0x0C 1..0=3
+unshfl     rd rs1 rs2 31..25=4  14..12=5 6..2=0x0C 1..0=3
+# Name conflict with rv_zbs' bext instruction
+#    bext       rd rs1 rs2 31..25=4  14..12=6 6..2=0x0C 1..0=3
+bdep       rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3
+packu      rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3
+bfp        rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3
+
+shfli      rd rs1 31..25=4 shamtw 14..12=1 6..2=0x04 1..0=3
+unshfli    rd rs1 31..25=4 shamtw 14..12=5 6..2=0x04 1..0=3

extensions/unratified/rv32_xcvmem

@@ -0,0 +1,31 @@
+# CORE-V Xcvmem extension: post-incrementing load & store operations
+# and register-register loads & store operations
+# Encodings as defined by OpenHW Group CV32E40P v1.3.2
+
+# Post-increment and reg-reg loads
+cv.lb.irpost  rd rs1 imm12             14..12=0 6..2=0x02 1..0=3
+cv.lbu.irpost rd rs1 imm12             14..12=4 6..2=0x02 1..0=3
+cv.lh.irpost  rd rs1 imm12             14..12=1 6..2=0x02 1..0=3
+cv.lhu.irpost rd rs1 imm12             14..12=5 6..2=0x02 1..0=3
+cv.lw.irpost  rd rs1 imm12             14..12=2 6..2=0x02 1..0=3
+cv.lb.rrpost  rd rs1 rs2   31..25=0x00 14..12=3 6..2=0x0A 1..0=3
+cv.lbu.rrpost rd rs1 rs2   31..25=0x08 14..12=3 6..2=0x0A 1..0=3
+cv.lh.rrpost  rd rs1 rs2   31..25=0x01 14..12=3 6..2=0x0A 1..0=3
+cv.lhu.rrpost rd rs1 rs2   31..25=0x09 14..12=3 6..2=0x0A 1..0=3
+cv.lw.rrpost  rd rs1 rs2   31..25=0x02 14..12=3 6..2=0x0A 1..0=3
+cv.lb.rr      rd rs1 rs2   31..25=0x04 14..12=3 6..2=0x0A 1..0=3
+cv.lbu.rr     rd rs1 rs2   31..25=0x0C 14..12=3 6..2=0x0A 1..0=3
+cv.lh.rr      rd rs1 rs2   31..25=0x05 14..12=3 6..2=0x0A 1..0=3
+cv.lhu.rr     rd rs1 rs2   31..25=0x0D 14..12=3 6..2=0x0A 1..0=3
+cv.lw.rr      rd rs1 rs2   31..25=0x06 14..12=3 6..2=0x0A 1..0=3
+
+# Post-increment and reg-reg stores
+cv.sb.irpost  rs1 rs2 imm12hi imm12lo              14..12=0 6..2=0x0A 1..0=3
+cv.sh.irpost  rs1 rs2 imm12hi imm12lo              14..12=1 6..2=0x0A 1..0=3
+cv.sw.irpost  rs1 rs2 imm12hi imm12lo              14..12=2 6..2=0x0A 1..0=3
+cv.sb.rrpost  rs1 rs2 prs3             31..25=0x10 14..12=3 6..2=0x0A 1..0=3
+cv.sh.rrpost  rs1 rs2 prs3             31..25=0x11 14..12=3 6..2=0x0A 1..0=3
+cv.sw.rrpost  rs1 rs2 prs3             31..25=0x12 14..12=3 6..2=0x0A 1..0=3
+cv.sb.rr      rs1 rs2 prs3             31..25=0x14 14..12=3 6..2=0x0A 1..0=3
+cv.sh.rr      rs1 rs2 prs3             31..25=0x15 14..12=3 6..2=0x0A 1..0=3
+cv.sw.rr      rs1 rs2 prs3             31..25=0x16 14..12=3 6..2=0x0A 1..0=3

extensions/unratified/rv32_xpulpabs

@@ -0,0 +1,3 @@
+# Xpulp extension subset: general ALU operations: abs
+
+p.abs    rd rs1      31..25=2  24..20=0 14..12=0 6..2=0x0C 1..0=3

extensions/unratified/rv32_xpulpbitop

@@ -0,0 +1,26 @@
+# Xpulp extension subset: bit manipulation operations & general ALU operations
+
+# INFO: overlaps with rv32_b
+# INFO: this is a superset of rv32_xpulpbitopsmall
+
+p.exths  rd rs1      31..25=8  24..20=0 14..12=4 6..2=0x0C 1..0=3
+p.exthz  rd rs1      31..25=8  24..20=0 14..12=5 6..2=0x0C 1..0=3
+p.extbs  rd rs1      31..25=8  24..20=0 14..12=6 6..2=0x0C 1..0=3
+p.extbz  rd rs1      31..25=8  24..20=0 14..12=7 6..2=0x0C 1..0=3
+
+p.extract    rd rs1 Luimm5 imm5   31..30=3 14..12=0 6..2=0x0C 1..0=3
+p.extractr   rd rs1 rs2  31..30=2 29..25=0 14..12=0 6..2=0x0C 1..0=3
+p.extractu   rd rs1 Luimm5 imm5   31..30=3 14..12=1 6..2=0x0C 1..0=3
+p.extractur  rd rs1 rs2  31..30=2 29..25=0 14..12=1 6..2=0x0C 1..0=3
+p.insert     rd rs1 Luimm5 imm5   31..30=3 14..12=2 6..2=0x0C 1..0=3
+p.insertr    rd rs1 rs2  31..30=2 29..25=0 14..12=2 6..2=0x0C 1..0=3
+p.bset       rd rs1 Luimm5 imm5   31..30=3 14..12=4 6..2=0x0C 1..0=3
+p.bsetr      rd rs1 rs2  31..30=2 29..25=0 14..12=4 6..2=0x0C 1..0=3
+p.bclr       rd rs1 Luimm5 imm5   31..30=3 14..12=3 6..2=0x0C 1..0=3
+p.bclrr      rd rs1 rs2  31..30=2 29..25=0 14..12=3 6..2=0x0C 1..0=3
+
+p.cnt    rd rs1 rs2  31..25=8           14..12=3 6..2=0x0C 1..0=3
+p.clb    rd rs1      31..25=8  24..20=0 14..12=2 6..2=0x0C 1..0=3
+p.fl1    rd rs1      31..25=8  24..20=0 14..12=1 6..2=0x0C 1..0=3
+p.ff1    rd rs1      31..25=8  24..20=0 14..12=0 6..2=0x0C 1..0=3
+p.ror    rd rs1      31..25=4  24..20=0 14..12=5 6..2=0x0C 1..0=3

extensions/unratified/rv32_xpulpbr

@@ -0,0 +1,4 @@
+# Xpulp extension subset: immediate branching operations
+
+p.beqimm rs1 imm5 bimm12hi bimm12lo 14..12=2 6..2=0x18 1..0=3
+p.bneimm rs1 imm5 bimm12hi bimm12lo 14..12=3 6..2=0x18 1..0=3

extensions/unratified/rv32_xpulpclip

@@ -0,0 +1,6 @@
+# Xpulp extension subset: general ALU operations: clip
+
+p.clip    rd rs1 imm5 31..25=10          14..12=1 6..2=0x0C 1..0=3
+p.clipr   rd rs1 rs2  31..25=10          14..12=5 6..2=0x0C 1..0=3
+p.clipu   rd rs1 imm5 31..25=10          14..12=2 6..2=0x0C 1..0=3
+p.clipur  rd rs1 rs2  31..25=10          14..12=6 6..2=0x0C 1..0=3

extensions/unratified/rv32_xpulphwloop

@@ -0,0 +1,10 @@
+# Xpulp extension subset: hardware loop operations
+
+# INFO: overlaps with rv_ipu
+
+lp.starti   L imm12               19..15=0 14..12=0 11..8=0 6..2=0x1E 1..0=3
+lp.endi     L imm12               19..15=0 14..12=1 11..8=0 6..2=0x1E 1..0=3
+lp.count    L rs1                 31..20=0 14..12=2 11..8=0 6..2=0x1E 1..0=3
+lp.counti   L imm12               19..15=0 14..12=3 11..8=0 6..2=0x1E 1..0=3
+lp.setup    L rs1 imm12           14..12=4 11..8=0 6..2=0x1E 1..0=3
+lp.setupi   L imm12 uimms         14..12=5 11..8=0 6..2=0x1E 1..0=3

extensions/unratified/rv32_xpulpmacsi

@@ -0,0 +1,4 @@
+# Xpulp extension subset: MAC operations
+
+p.mac rd rs1 rs2 31..25=33 14..12=0 6..2=0x0C 1..0=3
+p.msu rd rs1 rs2 31..25=33 14..12=1 6..2=0x0C 1..0=3

extensions/unratified/rv32_xpulpminmax

@@ -0,0 +1,10 @@
+# Xpulp extension subset: general ALU operations: min, max, avg
+
+# INFO: overlaps with rv32_b, rv_ipu
+
+p.min    rd rs1 rs2  31..25=2           14..12=4 6..2=0x0C 1..0=3
+p.minu   rd rs1 rs2  31..25=2           14..12=5 6..2=0x0C 1..0=3
+p.max    rd rs1 rs2  31..25=2           14..12=6 6..2=0x0C 1..0=3
+p.maxu   rd rs1 rs2  31..25=2           14..12=7 6..2=0x0C 1..0=3
+p.addN   rd rs1 rs2  31..30=0 Luimm5 14..12=2 6..2=0x16 1..0=3
+p.adduN  rd rs1 rs2  31..30=2 Luimm5 14..12=2 6..2=0x16 1..0=3

extensions/unratified/rv32_xpulppostmod

@@ -0,0 +1,32 @@
+# Xpulp extension subset: post-incrementing load & store operations
+# and register-register loads & store operations
+
+# INFO: overlaps with rv_frep, rv_ssr, rv_dma
+
+# Post-increment and reg-reg loads
+p.lb.irpost  rd rs1 imm12             14..12=0 6..2=0x02 1..0=3
+p.lbu.irpost rd rs1 imm12             14..12=4 6..2=0x02 1..0=3
+p.lh.irpost  rd rs1 imm12             14..12=1 6..2=0x02 1..0=3
+p.lhu.irpost rd rs1 imm12             14..12=5 6..2=0x02 1..0=3
+p.lw.irpost  rd rs1 imm12             14..12=2 6..2=0x02 1..0=3
+p.lb.rrpost  rd rs1 rs2   31..25=0x00 14..12=7 6..2=0x02 1..0=3
+p.lbu.rrpost rd rs1 rs2   31..25=0x20 14..12=7 6..2=0x02 1..0=3
+p.lh.rrpost  rd rs1 rs2   31..25=0x08 14..12=7 6..2=0x02 1..0=3
+p.lhu.rrpost rd rs1 rs2   31..25=0x28 14..12=7 6..2=0x02 1..0=3
+p.lw.rrpost  rd rs1 rs2   31..25=0x10 14..12=7 6..2=0x02 1..0=3
+p.lb.rr      rd rs1 rs2   31..25=0x00 14..12=7 6..2=0x00 1..0=3
+p.lbu.rr     rd rs1 rs2   31..25=0x20 14..12=7 6..2=0x00 1..0=3
+p.lh.rr      rd rs1 rs2   31..25=0x08 14..12=7 6..2=0x00 1..0=3
+p.lhu.rr     rd rs1 rs2   31..25=0x28 14..12=7 6..2=0x00 1..0=3
+p.lw.rr      rd rs1 rs2   31..25=0x10 14..12=7 6..2=0x00 1..0=3
+
+# Post-increment and reg-reg stores
+p.sb.irpost  rs1 rs2 imm12hi imm12lo              14..12=0 6..2=0x0A 1..0=3
+p.sh.irpost  rs1 rs2 imm12hi imm12lo              14..12=1 6..2=0x0A 1..0=3
+p.sw.irpost  rs1 rs2 imm12hi imm12lo              14..12=2 6..2=0x0A 1..0=3
+p.sb.rrpost  rs1 rs2 prs3             31..25=0x00 14..12=4 6..2=0x0A 1..0=3
+p.sh.rrpost  rs1 rs2 prs3             31..25=0x00 14..12=5 6..2=0x0A 1..0=3
+p.sw.rrpost  rs1 rs2 prs3             31..25=0x00 14..12=6 6..2=0x0A 1..0=3
+p.sb.rr      rs1 rs2 prs3             31..25=0x00 14..12=4 6..2=0x08 1..0=3
+p.sh.rr      rs1 rs2 prs3             31..25=0x00 14..12=5 6..2=0x08 1..0=3
+p.sw.rr      rs1 rs2 prs3             31..25=0x00 14..12=6 6..2=0x08 1..0=3

extensions/unratified/rv32_xpulpslet

@@ -0,0 +1,4 @@
+# Xpulp extension subset: general ALU operations: slet
+
+p.slet   rd rs1 rs2  31..25=2           14..12=2 6..2=0x0C 1..0=3
+p.sletu  rd rs1 rs2  31..25=2           14..12=3 6..2=0x0C 1..0=3