Add xCAUSE interrupt and exception code field masks - #427
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Andrew Waterman (aswaterman) merged 2 commits intoJul 30, 2026
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Define MCAUSE32/64_INT and MCAUSE32/64_EXCCODE for the Interrupt and Exception Code fields of mcause, plus XLEN-generic aliases in the __riscv_xlen selection block, following the same pattern used for MSTATUS_SD and SATP_MODE. scause and ucause share the identical bit layout per the privileged spec, so SCAUSE_* and UCAUSE_* are defined as aliases of the MCAUSE_* masks.
Luca Colagrande (colluca)
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## master #427 +/- ##
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- Coverage 97.08% 96.78% -0.30%
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Lines 926 933 +7
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Andrew Waterman (aswaterman)
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There is no ucause CSR, so we should remove those macros, but the rest of this LGTM.
There is no ucause CSR in the privileged spec, so the UCAUSE32/64_INT and UCAUSE32/64_EXCCODE masks (and the UCAUSE_INT/UCAUSE_EXCCODE xlen-generic aliases) don't apply. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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Thank you for the prompt review.
Good point, I fixed that now. |
Andrew Waterman (aswaterman)
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Jul 30, 2026
Andrew Waterman (aswaterman)
merged commit Jul 30, 2026
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Summary
MCAUSE32/64_INTandMCAUSE32/64_EXCCODEmasks for themcauseInterrupt and Exception Code fields, per the RISC-V privileged spec.MCAUSE_INT/MCAUSE_EXCCODEaliases in the__riscv_xlenselection block, following the same pattern already used forMSTATUS_SDandSATP_MODE.SCAUSE_*/UCAUSE_*equivalents, sincescause/ucauseshare the identical bit layout asmcause.