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Add xCAUSE interrupt and exception code field masks #427

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Merged
Andrew Waterman (aswaterman) merged 2 commits into from
Jul 30, 2026
Merged

Add xCAUSE interrupt and exception code field masks #427

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03b6774
Add MCAUSE/SCAUSE/UCAUSE Interrupt and Exception Code field masks
colluca Jul 29, 2026
c4958b5
Remove UCAUSE macros
colluca Jul 30, 2026
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18 changes: 18 additions & 0 deletions encoding.h
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Original file line number Diff line number Diff line change
Expand Up @@ -171,6 +171,16 @@

#define MIDELEG_FORCED_MASK MIP_HS_MASK

#define MCAUSE32_INT _RISCV_UL(0x80000000)
#define MCAUSE32_EXCCODE _RISCV_UL(0x7FFFFFFF)
#define MCAUSE64_INT _RISCV_ULL(0x8000000000000000)
#define MCAUSE64_EXCCODE _RISCV_ULL(0x7FFFFFFFFFFFFFFF)

#define SCAUSE32_INT MCAUSE32_INT
#define SCAUSE32_EXCCODE MCAUSE32_EXCCODE
#define SCAUSE64_INT MCAUSE64_INT
#define SCAUSE64_EXCCODE MCAUSE64_EXCCODE

#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP

Expand Down Expand Up @@ -521,11 +531,19 @@
# define SSTATUS_SD SSTATUS64_SD
# define RISCV_PGLEVEL_BITS 9
# define SATP_MODE SATP64_MODE
# define MCAUSE_INT MCAUSE64_INT
# define MCAUSE_EXCCODE MCAUSE64_EXCCODE
# define SCAUSE_INT SCAUSE64_INT
# define SCAUSE_EXCCODE SCAUSE64_EXCCODE
#else
# define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10
# define SATP_MODE SATP32_MODE
# define MCAUSE_INT MCAUSE32_INT
# define MCAUSE_EXCCODE MCAUSE32_EXCCODE
# define SCAUSE_INT SCAUSE32_INT
# define SCAUSE_EXCCODE SCAUSE32_EXCCODE
#endif
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
Expand Down
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