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feat(Zvdot4a8i): add extension and instruction data - #2015

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Maanvi212006:add-zvdot4a-extension
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feat(Zvdot4a8i): add extension and instruction data#2015
Maanvi212006 wants to merge 7 commits into
riscv:mainfrom
Maanvi212006:add-zvdot4a-extension

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Summary

Adds YAML data for the Zvdot4a extension (vector 4-element, 8-bit integer dot-product accumulate), previously known as Zvqdotq. The extension and its instructions were renamed following ARC feedback; see the discussion on #505 and the renaming PR riscv/riscv-opcodes#402.

This adds:

  • spec/std/isa/ext/Zvdot4a.yaml — extension definition
  • spec/std/isa/inst/Zvdot4a/ — all seven instructions:
    • vdot4a.vv / vdot4a.vx (signed × signed)
    • vdot4au.vv / vdot4au.vx (unsigned × unsigned)
    • vdot4asu.vv / vdot4asu.vx (signed vs2 × unsigned vs1/rs1)
    • vdot4aus.vx (unsigned vs2 × signed rs1 — vector-scalar only, since
      the vector-vector combination isn't separately encoded and can be
      obtained by swapping operand order into vdot4asu.vv)

Encodings were taken directly from the merged
riscv/riscv-opcodes#402 (extensions/unratified/rv_zvdot4a).

Notes for reviewers

  • operation() is left empty for all seven instructions, per the guidance in Add Zvdot4a8i extension #505 — happy to fill in IDL semantics in this PR or a
    follow-up if preferred.
  • requirements.extension is set to Zve32x (the minimal embedded vector base), by analogy with how Zve32f requires Zve32x. Please confirm this is the correct/intended prerequisite for this extension (as opposed to V).
  • state: development was used since the extension isn't ratified yet (target ratification 26Q4 per the RVI Jira ticket). Let me know if a different value is preferred.
  • Ratification/spec reference: [Zvdot4a8i] Extension for vector dot product (4-element, 8-bit integer) Version 0.1 riscv-isa-manual#2576.

Testing

  • rake test:inst_encodings — passed, no encoding conflicts.
  • rake gen:resolved_arch — resolves cleanly.
  • rake test:sorbet — no type errors.
  • rake test:udb:unit — full suite passes (3583 runs, 0 failures).

Closes #505

@codecov

codecov Bot commented Jul 26, 2026

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Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 68.51%. Comparing base (40ac592) to head (2d745b3).
⚠️ Report is 25 commits behind head on main.

Additional details and impacted files
@@           Coverage Diff           @@
##             main    #2015   +/-   ##
=======================================
  Coverage   68.51%   68.51%           
=======================================
  Files          53       53           
  Lines       27916    27918    +2     
  Branches     3620     3620           
=======================================
+ Hits        19126    19129    +3     
+ Misses       7269     7265    -4     
- Partials     1521     1524    +3     
Flag Coverage Δ
idlc 69.62% <ø> (+0.01%) ⬆️
udb 66.84% <ø> (-0.01%) ⬇️

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Maanvi212006 and others added 2 commits July 26, 2026 10:30
@ThinkOpenly

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I rebased this. It's very close to ready. CI is complaining about the "golden" instruction appendix not matching what would be generated with this PR merged. Please update:

./do chore:update_golden_appendix

Then commit, push here.

@jordancarlin

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I rebased this. It's very close to ready. CI is complaining about the "golden" instruction appendix not matching what would be generated with this PR merged. Please update:

./do chore:update_golden_appendix

Then commit, push here.

We should update the autofix job so that this is automatically updated in PRs. Many of the other golden files are already updated this way.

Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
@Maanvi212006

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Hi Jordan Carlin (@jordancarlin)
On your note about the autofix job — would it be alright if I took a stab at fixing that separately (bringing the golden instruction appendix in line with however the other golden files are auto-updated in PRs)? I don't want to step on it if it's already earmarked, but happy to file an issue and then open a PR for it if useful

@jordancarlin

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Maanvi212006 feel free to open a PR updating the autofix.ci workflow.

Comment thread spec/std/isa/ext/Zvdot4a.yaml Outdated
Maanvi212006 and others added 3 commits July 27, 2026 21:54
Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
@ThinkOpenly

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CI failing again due to the instruction appendix. Could you update that again?

Paul Clarke (ThinkOpenly) pushed a commit to AlgoArtist06/riscv-unified-db that referenced this pull request Aug 2, 2026
…#2183)

## Description
Adds a `do_gen_instruction_appendix_golden` step to `bin/chore`, wired
into `do_gen_all` (which the `autofix.ci` job already runs on every PR),
so `tests/golden/all_instructions.golden.adoc` gets regenerated
automatically alongside the other golden files (Xqci, cfg headers)
instead of requiring a manual `./do chore:update_golden_appendix` run.

Also adds a standalone `./bin/chore gen instruction-appendix` target for
convenience, matching the existing `xqci` / `cfg-headers` targets.

Came up on [riscv#2015](riscv#2015),
where a manual regen was needed to unblock CI:
riscv#2015 (comment)

Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
@ThinkOpenly

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need another rebase, or update the instruction appendix once more.

@ThinkOpenly Paul Clarke (ThinkOpenly) changed the title feat(Zvdot4a): add extension and instruction data feat(Zvdot4a8i): add extension and instruction data Aug 19, 2026
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Add Zvdot4a8i extension

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