feat(Zvdot4a8i): add extension and instruction data - #2015
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## main #2015 +/- ##
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Coverage 68.51% 68.51%
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Files 53 53
Lines 27916 27918 +2
Branches 3620 3620
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+ Hits 19126 19129 +3
+ Misses 7269 7265 -4
- Partials 1521 1524 +3
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Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
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I rebased this. It's very close to ready. CI is complaining about the "golden" instruction appendix not matching what would be generated with this PR merged. Please update: Then commit, push here. |
We should update the |
Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
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Hi Jordan Carlin (@jordancarlin) |
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Maanvi212006 feel free to open a PR updating the autofix.ci workflow. |
Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
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CI failing again due to the instruction appendix. Could you update that again? |
…#2183) ## Description Adds a `do_gen_instruction_appendix_golden` step to `bin/chore`, wired into `do_gen_all` (which the `autofix.ci` job already runs on every PR), so `tests/golden/all_instructions.golden.adoc` gets regenerated automatically alongside the other golden files (Xqci, cfg headers) instead of requiring a manual `./do chore:update_golden_appendix` run. Also adds a standalone `./bin/chore gen instruction-appendix` target for convenience, matching the existing `xqci` / `cfg-headers` targets. Came up on [riscv#2015](riscv#2015), where a manual regen was needed to unblock CI: riscv#2015 (comment) Signed-off-by: Maanvi212006 <maanvichetwani21@gmail.com>
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need another rebase, or update the instruction appendix once more. |
Summary
Adds YAML data for the Zvdot4a extension (vector 4-element, 8-bit integer dot-product accumulate), previously known as Zvqdotq. The extension and its instructions were renamed following ARC feedback; see the discussion on #505 and the renaming PR riscv/riscv-opcodes#402.
This adds:
spec/std/isa/ext/Zvdot4a.yaml— extension definitionspec/std/isa/inst/Zvdot4a/— all seven instructions:vdot4a.vv/vdot4a.vx(signed × signed)vdot4au.vv/vdot4au.vx(unsigned × unsigned)vdot4asu.vv/vdot4asu.vx(signed vs2 × unsigned vs1/rs1)vdot4aus.vx(unsigned vs2 × signed rs1 — vector-scalar only, sincethe vector-vector combination isn't separately encoded and can be
obtained by swapping operand order into
vdot4asu.vv)Encodings were taken directly from the merged
riscv/riscv-opcodes#402 (
extensions/unratified/rv_zvdot4a).Notes for reviewers
operation()is left empty for all seven instructions, per the guidance in Add Zvdot4a8i extension #505 — happy to fill in IDL semantics in this PR or afollow-up if preferred.
requirements.extensionis set toZve32x(the minimal embedded vector base), by analogy with howZve32frequiresZve32x. Please confirm this is the correct/intended prerequisite for this extension (as opposed toV).state: developmentwas used since the extension isn't ratified yet (target ratification 26Q4 per the RVI Jira ticket). Let me know if a different value is preferred.Testing
rake test:inst_encodings— passed, no encoding conflicts.rake gen:resolved_arch— resolves cleanly.rake test:sorbet— no type errors.rake test:udb:unit— full suite passes (3583 runs, 0 failures).Closes #505