Database systems · computer architecture · specialized hardware
I study how database execution changes when the compute substrate is specialized hardware. My current investigation explores analytical query execution on emerging accelerator platforms.
I am an undergraduate at the University of Michigan studying Computer Science and Mathematical Sciences, with a minor in Electrical Engineering.
Current investigation · Systems evidence · Research
Question. How should analytical operators, data layouts, and memory movement change when the execution substrate is a specialized accelerator?
What I am investigating. I study how database operators can be lowered into accelerator-native kernels, then examine tiling, layout, data movement, and execution behavior.
Evidence. Correctness checks, operator-level benchmarks, layout experiments, and hardware-aware execution traces.
Status. Active faculty-supervised systems research. Research code and unpublished measurements remain private while the work is in progress.
Methods. Python · SQL · Accelerator programming · Systems profiling
This conceptual output-stationary trace follows one complete 3×3 matrix multiplication. Blue A packets move right, amber B packets move down, and a white phase-lock ring appears only when an operand pair meets at a crosspoint. Each node locks three accumulator arcs before its teal output contact closes.
The active MAC envelope is 1 · 3 · 6 · 7 · 6 · 3 · 1; nine outputs become
ready in an anti-diagonal 1 · 2 · 3 · 2 · 1 wave. In total, the trace records
27 MAC events and 9 completed C values.
Conceptual cycle trace — not a physical accelerator floorplan.
The broader project is an iterative systems investigation, not a fixed linear pipeline. Measurements feed back into operator lowering, tiling, and layout.
Question. How much instruction-level parallelism can a compact pipeline extract while keeping hazards and forwarding understandable?
Built. A two-wide LC2K core with micro-op lowering, an eight-entry micro-op queue, a four-entry windowed issue engine, dual ALUs, one load/store-capable lane, and explicit writeback bypass paths.
Cycle-accurate playback from an RTL simulation of simple_add; short color rails identify instructions that entered decode together, while token outlines identify operation type. The initial I-cache fill is omitted and animation time is slowed for inspection. Topology is schematic, not a physical floorplan.
Evidence. Cycle-accurate memory-trace verification and gate-level synthesis under a 20 ns clock constraint.
Status. Completed course project; implementation is private.
Methods. SystemVerilog · VCS · Verdi · Synopsys Design Compiler
Question. Which invariants keep concurrent runtimes, network services, and virtual memory correct under interleaving and failure?
Built. A preemptive user-level thread library, a concurrent TCP file server with hand-over-hand read-write locking and crash-consistent updates, and a virtual memory manager with Clock replacement and copy-on-write fork.
Evidence. Adversarial concurrency tests, protocol validation, fault-path testing, and correctness traces.
Status. Completed systems coursework; implementations are private.
Methods. C++ · Linux · Threads · TCP · Virtual memory
Question. What is hidden behind the high-level interfaces of a Transformer implementation?
Built. BPE training and tokenization, embeddings, RMSNorm, SwiGLU, scaled dot-product attention, multi-head self-attention, RoPE, and Transformer blocks with reference-output tests.
Evidence. Coursework repository and visible implementation scope.
Status. Supporting coursework, not a current research focus.
Methods. Python · PyTorch · Transformers
I co-authored PANCDetect: Early Detection of Pancreatic Cancer from Multimodal EHR Data with LLM Embeddings, a preprint for which I contributed to clinical data preprocessing and analysis.
I work across operator semantics, systems implementation, profiling, benchmarking, memory-layout analysis, and accelerator kernels. The easiest way to reach me is through LinkedIn or email.