Become a sponsor to veryl-lang

What is Veryl?

Veryl is an open-source hardware description language (HDL) built as a modern
alternative to SystemVerilog. It keeps a familiar foundation for SystemVerilog
engineers while offering a cleaner, safer, and more productive way to design
hardware. Veryl transpiles to human-readable SystemVerilog, so it drops into
existing toolchains and projects without lock-in.

Why Veryl?

• Optimized syntax — A syntax tuned for logic design, with guaranteed
  synthesizability, consistent simulation results, and simplifications for
  common idioms. Easy to learn, reliable to write.
• Interoperability — Designed to integrate with SystemVerilog. The
  transpiled output stays readable, enabling smooth partial adoption and
  straightforward debugging.
• Productivity — A rich toolchain out of the box: package manager, build
  tools, real-time checkers for VSCode / Vim / Emacs, autocompletion, and
  automatic formatting.

Why support us?

Veryl is free and open source, and it is used in real hardware projects. Your
contribution keeps the project healthy and independent.

Today, contributions go toward:

• Infrastructure — continuous integration (CI) and domain renewals that keep
  the website, documentation, and services running.

As the project grows, we plan to put contributions toward:

• Development & maintenance — sustaining the ongoing work of reviewing
  contributions, fixing bugs, and shipping regular releases.
• Outreach — travel to conferences and meetups to present Veryl and expand
  its community.

Every contribution — large or small — directly helps make hardware design more
open and productive. Thank you for supporting Veryl.