fix(solis): probe the slot current ceiling the inverter enforces but does not report

[springfall2008]

Follow-up to #5187 / #5189 (and builds on #5308).

Problem

A 3.6 kW S5-EH1P3.6K-L (model 3102, firmware 4C0050, TOU V2, one PYLON_LV pack) reports 100 A in CID 7224/7226. #5189 capped slot currents at the 75 A rated current (3600 W / 48 V), but the inverter refuses anything above 60 A. A refused write leaves the register at its old value, so every discharge slot sat at 0 A and held the battery through each planned export. The planner meanwhile assumed 4.8 kW each way (the raw register × 48 V).

Live testing on that inverter, using the new CLI below, showed:

• 60 A is kept; 61, 62, 65, 70, 71 and 75 A are refused
• the same holds for charge and discharge, and on enabled (slot 1, window open) and disabled (slot 6) slots alike
• no API reply reports 60 A:
  • atRead/atReadBatch return only msg/yuanzhi/command/needLoop, with no min/max, so the existing sysCommand.max check never fires on the OAuth route
  • inverterDetail's batteryC/DMaxiSet read 65 A and the BMS limits read 160 A

A second inverter, an 8 kW hybrid on a 51.2 V pack, reads 180 A there and ran its slots at 180 A before #5189. The rated estimate (8000 W / 51.2 V = 156 A) has held it at 156 A since then, capping PV charging. So the rated estimate is wrong in both directions, and the cap has to be measured.

Change

Slot current ceiling probe (ensure_slot_current_probed()). Predbat only drives slot 1. On first discovery, with control enabled and TOU V2 firmware, it picks a slot from 2–6 that is disabled in both directions, and for each direction:

1. writes the battery-side cap: the CID 7224/7226 register, lowered by any slot metadata. The rated estimate plays no part.
2. if that is refused, steps down 5 A at a time until one is kept
3. then steps up 1 A at a time until one is refused, or until the battery-side cap is reached. That gives the exact ceiling, and nothing above the register is ever written.
4. restores the slot's original value

Guarding against an offline or erroring inverter:

• A refusal is concluded only when the write is acknowledged and the settled read-back still holds the previous value.
• A read-back still holding the old value gets one more settle before it counts as a refusal, so a slow relay is not saved as a lower ceiling.
• Any error, no reply, an offline datalogger or an unexpected read-back gives no verdict. The probe is then abandoned and nothing is learned. It is retried after 1 h, and the wait doubles on each further failure up to a day, so an inverter that never gives a verdict is not probed every hour indefinitely.
• Refusing everything down to 10 A also learns nothing. An unreachable inverter can never settle on a minimum.

When it runs:

• The probe runs last in each cycle, after the control writes, the publish and auto-config, so a first probe never delays slot-1 control.
• It honours switch.<prefix>_set_read_only. While read-only is on it stays pending, and it runs on the first cycle after read-only is turned off.
• It waits until the saved ceilings have loaded, so a transient storage error cannot trigger a fresh probe that overwrites them.

The result is saved through Storage (solis/slot_current_limits) and reloaded. It is semi-static:

• A new inverter is probed at once.
• A known one is re-checked only once its result is a day old. The re-check starts from the known ceiling, so an unchanged one costs two writes plus the restore.
• A failed re-check keeps the known value.

slot_current_limits() applies the measured ceiling to every slot write, and it replaces the #5189 rated estimate. The rated estimate is only a fallback until an inverter has been probed. inverter_limit still bounds the AC side in the plan.

Planner limits. New sensor.<prefix>_solis_<sn>_slot_charge_power_max / _slot_discharge_power_max sensors (slot cap × nominal voltage) are published. They now feed inverter_limit_charge/_discharge (still overwrite=False, so an apps.yaml value wins) and battery_rate_max. These replace the raw 4800 W register figures from #5308. The slot power sliders' max follows too. max_charge_power/max_discharge_power still show the register.

Diagnostics:

• A new slot_current_limits() helper returns every input to the V2 cap. The write path gets the same result as before.
• A limits line, logged when it changes, names which input set each cap (charge 60.0A from the probed ceiling (register 100A, no slot metadata max, probed max 60.0A) …).
• The stale per-cycle Capping slot currents … at 75.0A line is removed.
• An allow-listed inverter summary line (model/firmware/rating/packs) is logged; the station name and address stay out.
• "Calculated max currents" now names register × packs vs the default.
• Each probe verdict is logged.

CLI harness (solis.py __main__), used to find all this:

• --config apps.yaml, resolving !secret from a secrets.yaml beside the file. Its key map is kept in step with COMPONENT_LIST by a test.
• OAuth plus the Supabase refresh settings, and --inverter-sn
• --dump-raw, which prints every reply in full via a response_observer hook that is off in production
• --probe-ceiling, which runs the production probe on its own. It needs --write, and run() stays read-only while it runs. The manual any-slot probe used during the investigation has been removed in favour of this.

Testing

• 23 new tests in test_solis.py. They cover:
  • the probe's exact-ceiling search from the register
  • an accepted battery limit replacing a lower rated estimate
  • offline and write-error cases learning nothing
  • refuse-everything learning nothing
  • the Storage round trip, a daily re-check starting at the known ceiling (two writes when unchanged), a failed re-check keeping the value, and an unreadable saved entry
  • the skip conditions and slot choice
  • read-only keeping the probe pending, retry backoff, a slow relay's second settle, a load that fails or finds malformed data, unreadable registers not stopping the publish, a moving HV voltage not re-logging the limits line, and the probe running after the control write and publish
  • published limits before a probe (the rated fallback, 3600 W), after it (2880 W), and with a measured ceiling above the rated estimate
  • the limits line and change-only logging
  • the inverter-summary allow-list
  • CLI key and merge behaviour, and !secret resolution
  • the response observer
• The probe tests fail without the probe code (checked by stashing the source) and pass with it. The seven review-fix tests each fail against the code before the fixes, for the reason they target (read-only made 86 requests; a junk register raised ValueError; the probe ran before the control write), and pass with them.
• ./run_all --quick passes, and pre-commit passes on the changed files.
• Live, with full --write runs:
  • 3.6 kW: probed slot 6 and learned 60/60 A. The write pass then capped at 60 A, and inverter_limit_charge/_discharge/battery_rate_max read 2880 W.
  • 8 kW: re-run after the start point moved to the register, and the result was confirmed.

Notes

• Blast radius: GitNexus rates SolisAPI.run, write_time_windows_if_changed and fetch_inverter_details LOW, with a single caller each. The index is stale for the new helpers, so their callers were checked by search. Everything is inside solis.py; inverter.py is untouched.
• Not covered: re-probing on a firmware change, and V1 (CID 103) inverters, which have no per-slot current registers and are not probed.
• Cost: a first probe on an inverter like the 3.6 kW one walks down from 100 A. That is about eight refused writes per direction and roughly two minutes, most of it the 5 s settle after each refusal. After that, the daily re-check is two writes plus the restore per direction.
• A refused slot-1 write does not trigger an early re-probe. A ceiling that drops is picked up at the next daily re-check.
• tools/debug-journal.md's Solis row still points at the removed Capping slot currents line and at the sysCommand slot metadata. It can be refreshed once this merges.

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