@@ -86,7 +86,8 @@ typedef struct
8686 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_SRAM2_PE,
8787 @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_NSWBOOT0,
8888 @ref FLASH_OB_USER_NBOOT0, @ref FLASH_OB_USER_IO_VDD_HSLV,
89- @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN */
89+ @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN
90+ @ref FLASH_OB_USER_SRAM3_PE */
9091#if defined (CPU_IN_SECURE_STATE )
9192 uint32_t WMSecConfig ; /*!< Configuration of the Watermark-based Secure Area (used for @ref OPTIONBYTE_WMSEC).
9293 This parameter must be a value of @ref FLASH_OB_WMSEC */
@@ -338,20 +339,33 @@ typedef struct
338339#define OB_USER_SWAP_BANK FLASH_OPTR_SWAP_BANK /*!< Swap banks */
339340#define OB_USER_DUALBANK FLASH_OPTR_DUALBANK /*!< Dual-Bank on 1MB/512kB Flash memory devices */
340341#define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check enable */
342+ #if defined(FLASH_OPTR_SRAM3_PE )
343+ #define OB_USER_SRAM3_PE FLASH_OPTR_SRAM3_PE /*!< SRAM3 parity check enable */
344+ #endif /* FLASH_OPTR_SRAM3_PE */
341345#define OB_USER_SRAM2_RST FLASH_OPTR_SRAM2_RST /*!< SRAM2 erase when system reset */
342346#define OB_USER_NSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */
343347#define OB_USER_NBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */
344348#define OB_USER_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV /*!< High speed IO at low VDD voltage configuration bit */
345349#define OB_USER_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV /*!< High speed IO at low VDDIO2 voltage configuration bit */
346350#define OB_USER_TZEN FLASH_OPTR_TZEN /*!< Global TrustZone security enable */
347351
352+ #if defined(FLASH_OPTR_SRAM3_PE )
353+ #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BDRST_POR | OB_USER_NRST_STOP | \
354+ OB_USER_NRST_STDBY | OB_USER_NRST_SHDW | OB_USER_SRAM1_RST | \
355+ OB_USER_IWDG_SW | OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | \
356+ OB_USER_WWDG_SW | OB_USER_SWAP_BANK | OB_USER_DUALBANK | \
357+ OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | OB_USER_NSWBOOT0 | \
358+ OB_USER_NBOOT0 | OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | \
359+ OB_USER_TZEN | OB_USER_SRAM3_PE) /*!< All User option bits */
360+ #else
348361#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BDRST_POR | OB_USER_NRST_STOP | \
349362 OB_USER_NRST_STDBY | OB_USER_NRST_SHDW | OB_USER_SRAM1_RST | \
350363 OB_USER_IWDG_SW | OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | \
351364 OB_USER_WWDG_SW | OB_USER_SWAP_BANK | OB_USER_DUALBANK | \
352365 OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | OB_USER_NSWBOOT0 | \
353366 OB_USER_NBOOT0 | OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | \
354367 OB_USER_TZEN) /*!< All User option bits */
368+ #endif /* FLASH_OPTR_SRAM3_PE */
355369/**
356370 * @}
357371 */
@@ -472,6 +486,18 @@ typedef struct
472486 */
473487#define OB_SRAM2_PE_ENABLE 0x00000000U /*!< SRAM2 Parity check enable */
474488#define OB_SRAM2_PE_DISABLE FLASH_OPTR_SRAM2_PE /*!< SRAM2 Parity check disable */
489+ /**
490+ * @}
491+ */
492+
493+ #if defined(FLASH_OPTR_SRAM3_PE )
494+ /** @defgroup FLASH_OB_USER_SRAM3_PE FLASH Option Bytes User SRAM3 Parity Check Enable
495+ * @{
496+ */
497+ #define OB_SRAM3_PE_ENABLE 0x00000000U /*!< SRAM3 Parity check enable */
498+ #define OB_SRAM3_PE_DISABLE FLASH_OPTR_SRAM3_PE /*!< SRAM3 Parity check disable */
499+ #endif /* FLASH_OPTR_SRAM3_PE */
500+
475501/**
476502 * @}
477503 */
@@ -1160,6 +1186,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
11601186
11611187#define IS_OB_USER_SRAM2_PE (VALUE ) (((VALUE) == OB_SRAM2_PE_ENABLE) || ((VALUE) == OB_SRAM2_PE_DISABLE))
11621188
1189+ #if defined(FLASH_OPTR_SRAM3_PE )
1190+ #define IS_OB_USER_SRAM3_PE (VALUE ) (((VALUE) == OB_SRAM3_PE_ENABLE) || ((VALUE) == OB_SRAM3_PE_DISABLE))
1191+ #endif /* FLASH_OPTR_SRAM3_PE */
1192+
11631193#define IS_OB_USER_SRAM2_RST (VALUE ) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
11641194
11651195#define IS_OB_USER_SWBOOT0 (VALUE ) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
0 commit comments