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variants(h5): add generic H523R(C-E)T and C533RET
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 4ee32c3 commit 4fbdb3d

4 files changed

Lines changed: 306 additions & 3 deletions

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‎README.md‎

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Original file line numberDiff line numberDiff line change
@@ -595,6 +595,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32H503CB | Generic Board | *2.9.0* | |
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| :green_heart: | STM32H503KB | Generic Board | *2.8.1* | |
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| :green_heart: | STM32H503RB | Generic Board | *2.7.0* | |
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| :yellow_heart: | STM32H523RC<br>STM32H523RE | Generic Board | **3.0.1** | |
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| :yellow_heart: | STM32H533RE | Generic Board | **3.0.1** | |
598600
| :green_heart: | STM32H562RGT | WeAct H562RGT | *2.9.0* | |
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| :green_heart: | STM32H562RGT<br>STM32H562RIT | Generic Board | *2.9.0* | |
600602
| :green_heart: | STM32H562RGV<br>STM32H562RIV | Generic Board | *3.0.0* | |

‎boards.txt‎

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9507,6 +9507,33 @@ GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx
95079507
GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT
95089508
GenH5.menu.pnum.GENERIC_H503RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd
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9510+
# Generic H523RCTx
9511+
GenH5.menu.pnum.GENERIC_H523RCTX=Generic H523RCTx
9512+
GenH5.menu.pnum.GENERIC_H523RCTX.upload.maximum_size=262144
9513+
GenH5.menu.pnum.GENERIC_H523RCTX.upload.maximum_data_size=278528
9514+
GenH5.menu.pnum.GENERIC_H523RCTX.build.board=GENERIC_H523RCTX
9515+
GenH5.menu.pnum.GENERIC_H523RCTX.build.product_line=STM32H523xx
9516+
GenH5.menu.pnum.GENERIC_H523RCTX.build.variant=STM32H5xx/H523R(C-E)T_H533RET
9517+
GenH5.menu.pnum.GENERIC_H523RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H523.svd
9518+
9519+
# Generic H523RETx
9520+
GenH5.menu.pnum.GENERIC_H523RETX=Generic H523RETx
9521+
GenH5.menu.pnum.GENERIC_H523RETX.upload.maximum_size=524288
9522+
GenH5.menu.pnum.GENERIC_H523RETX.upload.maximum_data_size=278528
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GenH5.menu.pnum.GENERIC_H523RETX.build.board=GENERIC_H523RETX
9524+
GenH5.menu.pnum.GENERIC_H523RETX.build.product_line=STM32H523xx
9525+
GenH5.menu.pnum.GENERIC_H523RETX.build.variant=STM32H5xx/H523R(C-E)T_H533RET
9526+
GenH5.menu.pnum.GENERIC_H523RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H523.svd
9527+
9528+
# Generic H533RETx
9529+
GenH5.menu.pnum.GENERIC_H533RETX=Generic H533RETx
9530+
GenH5.menu.pnum.GENERIC_H533RETX.upload.maximum_size=524288
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GenH5.menu.pnum.GENERIC_H533RETX.upload.maximum_data_size=278528
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GenH5.menu.pnum.GENERIC_H533RETX.build.board=GENERIC_H533RETX
9533+
GenH5.menu.pnum.GENERIC_H533RETX.build.product_line=STM32H533xx
9534+
GenH5.menu.pnum.GENERIC_H533RETX.build.variant=STM32H5xx/H523R(C-E)T_H533RET
9535+
GenH5.menu.pnum.GENERIC_H533RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H533.svd
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# Generic H562RGTx
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GenH5.menu.pnum.GENERIC_H562RGTX=Generic H562RGTx
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GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_size=1048576
@@ -17752,4 +17779,4 @@ Phoque.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float
1775217779
Phoque.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf
1775317780
Phoque.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float
1775417781
Phoque.menu.rtlib.full=Newlib Standard
17755-
Phoque.menu.rtlib.full.build.flags.ldspecs=
17782+
Phoque.menu.rtlib.full.build.flags.ldspecs=

‎variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c‎

Lines changed: 87 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,93 @@
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*/
2222
WEAK void SystemClock_Config(void)
2323
{
24-
/* SystemClock_Config can be generated by STM32CubeMX */
25-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
24+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
25+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
26+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
27+
28+
/** Configure the main internal regulator output voltage
29+
*/
30+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
31+
32+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
33+
34+
/** Initializes the RCC Oscillators according to the specified parameters
35+
* in the RCC_OscInitTypeDef structure.
36+
*/
37+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
38+
| RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI;
39+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
40+
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2;
41+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
42+
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.CSIState = RCC_CSI_ON;
45+
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
47+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
48+
RCC_OscInitStruct.PLL.PLLM = 1;
49+
RCC_OscInitStruct.PLL.PLLN = 125;
50+
RCC_OscInitStruct.PLL.PLLP = 2;
51+
RCC_OscInitStruct.PLL.PLLQ = 4;
52+
RCC_OscInitStruct.PLL.PLLR = 2;
53+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
54+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
55+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
56+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
57+
Error_Handler();
58+
}
59+
60+
/** Initializes the CPU, AHB and APB buses clocks
61+
*/
62+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
63+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
64+
| RCC_CLOCKTYPE_PCLK3;
65+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
66+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
67+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
68+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
69+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
70+
71+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
72+
Error_Handler();
73+
}
74+
75+
/** Initializes the peripherals clock
76+
*/
77+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1
78+
| RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1
79+
| RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3
80+
| RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_USB;
81+
82+
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK;
83+
PeriphClkInitStruct.DacLowPowerClockSelection = RCC_DACLPCLKSOURCE_LSI;
84+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
85+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
86+
PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q;
87+
PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q;
88+
PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q;
89+
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
90+
PeriphClkInitStruct.PLL2.PLL2M = 1;
91+
PeriphClkInitStruct.PLL2.PLL2N = 96;
92+
PeriphClkInitStruct.PLL2.PLL2P = 2;
93+
PeriphClkInitStruct.PLL2.PLL2Q = 4;
94+
PeriphClkInitStruct.PLL2.PLL2R = 2;
95+
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
96+
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
97+
PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
98+
PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ;
99+
PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL2Q;
100+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
101+
102+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
103+
Error_Handler();
104+
}
105+
106+
107+
108+
/** Configure the programming delay
109+
*/
110+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
26111
}
27112

28113
#endif /* ARDUINO_GENERIC_* */
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1+
/*
2+
******************************************************************************
3+
**
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** @file : LinkerScript.ld
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**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
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** @brief : Linker script for STM32H533RETx Device from STM32H5 series
9+
** 512KBytes FLASH
10+
** 272KBytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
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**
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** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
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** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
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**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2026 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
_sstack = _estack - _Min_Stack_Size;
41+
42+
_Min_Heap_Size = 0x200; /* required amount of heap */
43+
_Min_Stack_Size = 0x400; /* required amount of stack */
44+
45+
/* Memories definition */
46+
MEMORY
47+
{
48+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
49+
FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
50+
}
51+
52+
/* Sections */
53+
SECTIONS
54+
{
55+
56+
/* The startup code into "FLASH" Rom type memory */
57+
.isr_vector :
58+
{
59+
. = ALIGN(4);
60+
KEEP(*(.isr_vector)) /* Startup code */
61+
. = ALIGN(4);
62+
} >FLASH
63+
64+
/* The program code and other data into "FLASH" Rom type memory */
65+
.text :
66+
{
67+
. = ALIGN(4);
68+
*(.text) /* .text sections (code) */
69+
*(.text*) /* .text* sections (code) */
70+
*(.glue_7) /* glue arm to thumb code */
71+
*(.glue_7t) /* glue thumb to arm code */
72+
*(.eh_frame)
73+
74+
KEEP (*(.init))
75+
KEEP (*(.fini))
76+
77+
. = ALIGN(4);
78+
_etext = .; /* define a global symbols at end of code */
79+
} >FLASH
80+
81+
/* Constant data into "FLASH" Rom type memory */
82+
.rodata :
83+
{
84+
. = ALIGN(4);
85+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
86+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
88+
} >FLASH
89+
90+
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
91+
{
92+
. = ALIGN(4);
93+
*(.ARM.extab* .gnu.linkonce.armextab.*)
94+
. = ALIGN(4);
95+
} >FLASH
96+
97+
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
98+
{
99+
. = ALIGN(4);
100+
__exidx_start = .;
101+
*(.ARM.exidx*)
102+
__exidx_end = .;
103+
. = ALIGN(4);
104+
} >FLASH
105+
106+
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
107+
{
108+
. = ALIGN(4);
109+
PROVIDE_HIDDEN (__preinit_array_start = .);
110+
KEEP (*(.preinit_array*))
111+
PROVIDE_HIDDEN (__preinit_array_end = .);
112+
. = ALIGN(4);
113+
} >FLASH
114+
115+
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
116+
{
117+
. = ALIGN(4);
118+
PROVIDE_HIDDEN (__init_array_start = .);
119+
KEEP (*(SORT(.init_array.*)))
120+
KEEP (*(.init_array*))
121+
PROVIDE_HIDDEN (__init_array_end = .);
122+
. = ALIGN(4);
123+
} >FLASH
124+
125+
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
126+
{
127+
. = ALIGN(4);
128+
PROVIDE_HIDDEN (__fini_array_start = .);
129+
KEEP (*(SORT(.fini_array.*)))
130+
KEEP (*(.fini_array*))
131+
PROVIDE_HIDDEN (__fini_array_end = .);
132+
. = ALIGN(4);
133+
} >FLASH
134+
135+
/* Used by the startup to initialize data */
136+
_sidata = LOADADDR(.data);
137+
138+
/* Initialized data sections into "RAM" Ram type memory */
139+
.data :
140+
{
141+
. = ALIGN(4);
142+
_sdata = .; /* create a global symbol at data start */
143+
*(.data) /* .data sections */
144+
*(.data*) /* .data* sections */
145+
*(.RamFunc) /* .RamFunc sections */
146+
*(.RamFunc*) /* .RamFunc* sections */
147+
148+
. = ALIGN(4);
149+
_edata = .; /* define a global symbol at data end */
150+
151+
} >RAM AT> FLASH
152+
153+
/* Uninitialized data section into "RAM" Ram type memory */
154+
. = ALIGN(4);
155+
.bss :
156+
{
157+
/* This is used by the startup in order to initialize the .bss section */
158+
_sbss = .; /* define a global symbol at bss start */
159+
__bss_start__ = _sbss;
160+
*(.bss)
161+
*(.bss*)
162+
*(COMMON)
163+
164+
. = ALIGN(4);
165+
_ebss = .; /* define a global symbol at bss end */
166+
__bss_end__ = _ebss;
167+
} >RAM
168+
169+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
170+
._user_heap_stack :
171+
{
172+
. = ALIGN(8);
173+
PROVIDE ( end = . );
174+
PROVIDE ( _end = . );
175+
. = . + _Min_Heap_Size;
176+
. = . + _Min_Stack_Size;
177+
. = ALIGN(8);
178+
} >RAM
179+
180+
/* Remove information from the compiler libraries */
181+
/DISCARD/ :
182+
{
183+
libc.a ( * )
184+
libm.a ( * )
185+
libgcc.a ( * )
186+
}
187+
188+
.ARM.attributes 0 : { *(.ARM.attributes) }
189+
}

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