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variants(h5): add Nucleo-H533RE
Fixes #3062. Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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‎README.md‎

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@@ -153,6 +153,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* | |
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| :green_heart: | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* | |
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| :green_heart: | STM32H503RB | [Nucleo H503RB](https://www.st.com/en/evaluation-tools/nucleo-h503rb.html) | *2.7.0* | |
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| :yellow_heart: | STM32H533RE | [Nucleo H533RE](https://www.st.com/en/evaluation-tools/nucleo-h533re.html) | **3.0.1** | |
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| :green_heart: | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | *2.1.0* | |
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| :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | |
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| :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | |

‎boards.txt‎

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@@ -803,6 +803,21 @@ Nucleo_64.menu.pnum.NUCLEO_H503RB.build.variant=STM32H5xx/H503RBT
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Nucleo_64.menu.pnum.NUCLEO_H503RB.openocd.target=stm32h5x
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Nucleo_64.menu.pnum.NUCLEO_H503RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd
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# NUCLEO H533RE
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Nucleo_64.menu.pnum.NUCLEO_H533RE=Nucleo H533RE
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Nucleo_64.menu.pnum.NUCLEO_H533RE.node=NOD_H533RE
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Nucleo_64.menu.pnum.NUCLEO_H533RE.upload.maximum_size=524288
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Nucleo_64.menu.pnum.NUCLEO_H533RE.upload.maximum_data_size=278528
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Nucleo_64.menu.pnum.NUCLEO_H533RE.build.mcu=cortex-m33
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Nucleo_64.menu.pnum.NUCLEO_H533RE.build.fpu=-mfpu=fpv5-sp-d16
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Nucleo_64.menu.pnum.NUCLEO_H533RE.build.float-abi=-mfloat-abi=hard
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Nucleo_64.menu.pnum.NUCLEO_H533RE.build.board=NUCLEO_H533RE
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Nucleo_64.menu.pnum.NUCLEO_H533RE.build.series=STM32H5xx
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Nucleo_64.menu.pnum.NUCLEO_H533RE.build.product_line=STM32H533xx
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Nucleo_64.menu.pnum.NUCLEO_H533RE.build.variant=STM32H5xx/H523R(C-E)T_H533RET
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Nucleo_64.menu.pnum.NUCLEO_H533RE.openocd.target=stm32h5x
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Nucleo_64.menu.pnum.NUCLEO_H533RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H533.svd
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# NUCLEO_L010RB board
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Nucleo_64.menu.pnum.NUCLEO_L010RB=Nucleo L010RB
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Nucleo_64.menu.pnum.NUCLEO_L010RB.node=NODE_L010RB
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/*
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*******************************************************************************
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* Copyright (c) 2020-2026, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#if defined(ARDUINO_NUCLEO_H533RE)
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#include "pins_arduino.h"
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// Digital PinName array
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const PinName digitalPin[] = {
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PB_15, //D0
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PB_14, //D1
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PC_8, //D2
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PB_3, //D3
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PB_5, //D4
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PB_4, //D5
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PB_10, //D6
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PA_8, //D7
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PC_7, //D8
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PC_6, //D9
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PC_9, //D10
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PA_7, //D11/A10
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PA_6, //D12A11
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PA_5, //D13/A12
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PB_7, //D14
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PB_6, //D15
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PC_10, //D16
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PC_12, //D17
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PA_13, //D18
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PA_14, //D19
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PA_15, //D20
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PC_13, //D21
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PC_14, //D22
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PC_15, //D23
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PH_0, //D24
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PH_1, //D25
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PC_2, //D26/A6
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PC_3, //D27/A7
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PC_11, //D28
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PD_2, //D29
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PA_0, //D30/A0
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PA_1, //D31/A1
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PB_1, //D32/A2
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PB_0, //D33/A3
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PC_1, //D34/A4
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PC_0, //D35/A5
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PA_9, //D36
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PA_10, //D37
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PC_5, //D38/A8
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PA_12, //D39
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PA_11, //D40
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PB_12, //D41
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PB_2, //D42
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PB_15, //D43
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PB_14, //D44
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PB_13, //D45
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PC_4, //D46/A9
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PB_8, //D47
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PA_2, //D48/A13
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PA_3, //D49/A14
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PA_4 //D50/A15
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};
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// Analog (Ax) pin number array
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const pin_size_t analogInputPin[] = {
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30, // A0, PA0
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31, // A1, PA1
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32, // A2, PB1
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33, // A3, PB0
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34, // A4, PC1
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35, // A5, PC0
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26, // A6, PC2
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27, // A7, PC3
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38, // A8, PC5
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46, // A9, PC4
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11, // A10, PA7
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12, // A11, PA6
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13, // A12, PA5
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48, // A13, PA2
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49, // A14, PA3
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50 // A15, PA4
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief System Clock Configuration
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* @param None
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* @retval None
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*/
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WEAK void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
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RCC_CRSInitTypeDef RCC_CRSInitStruct = {};
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/* Configure the main internal regulator output voltage */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
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while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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/** Configure LSE Drive Capability
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* Warning : Only applied when the LSE is disabled.
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
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| RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 6;
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RCC_OscInitStruct.PLL.PLLN = 125;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 4;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/* Initializes the CPU, AHB and APB buses clocks */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
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| RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
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Error_Handler();
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}
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/* Initializes the peripherals clock */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC
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| RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SDMMC1
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| RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2
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| RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4
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| RCC_PERIPHCLK_USB;;
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PeriphClkInitStruct.DacLowPowerClockSelection = RCC_DACLPCLKSOURCE_LSE;
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PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK;
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PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
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PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
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PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q;
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PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q;
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PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q;
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PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE;
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PeriphClkInitStruct.PLL2.PLL2M = 6;
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PeriphClkInitStruct.PLL2.PLL2N = 125;
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PeriphClkInitStruct.PLL2.PLL2P = 2;
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PeriphClkInitStruct.PLL2.PLL2Q = 4;
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PeriphClkInitStruct.PLL2.PLL2R = 2;
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PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
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PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ;
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PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL2Q;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/* Enable the CRS APB clock */
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__HAL_RCC_CRS_CLK_ENABLE();
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/* Configures CRS */
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RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
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RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_LSE;
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RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
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RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 32768);
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RCC_CRSInitStruct.ErrorLimitValue = 34;
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RCC_CRSInitStruct.HSI48CalibrationValue = 32;
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HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
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/* Configure the programming delay */
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__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARDUINO_NUCLEO_H533RE */

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