chore(variants): update custom peripheral pin mapping

to accommodate changes in the XSPI peripheral pin mapping.

Signed-off-by: Frederic Pillon <frederic.pillon@st.com>

Author: fpistm

variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins_PYBSTICK26_PRO.c

@@ -319,7 +319,7 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // QUADSPI_BK1_NCS
   // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}

variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins_DISCO_F413ZH.c

@@ -450,7 +450,7 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   // {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // QUADSPI_BK1_NCS
   // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
   {PG_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // QUADSPI_BK1_NCS

variants/STM32F4xx/F446V(C-E)T/PeripheralPins_FYSETC_S6.c

@@ -395,7 +395,7 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   // {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
   // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}

variants/STM32F4xx/F446V(C-E)T/PeripheralPins_RUMBA32.c

@@ -395,7 +395,7 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   // {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
   // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}

variants/STM32F4xx/F446V(C-E)T/PeripheralPins_VAKE_V1.c

@@ -423,7 +423,7 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   // {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
   // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}

variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins_DISCO_F723IE.c

@@ -474,8 +474,14 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS (on-board flash)
+  {NC,    NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_NCS2[] = {
   {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}
 };

variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins_ETHERCAT_DUINO.c

@@ -467,7 +467,7 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
   // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}

variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins_F7x6ZG.c

@@ -453,8 +453,14 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+  {NC,    NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_NCS2[] = {
   {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}
 };

variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins_DISCO_F746NG.c

@@ -501,8 +501,14 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+  {NC,    NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_NCS2[] = {
   {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
   {NC,    NP,      0}
 };

variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins_REMRAM_V1.c

@@ -459,7 +459,7 @@ WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
 #endif
 
 #ifdef HAL_QSPI_MODULE_ENABLED
-WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+WEAK const PinMap PinMap_QUADSPI_NCS1[] = {
   // {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
   // {PB_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS
   // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS